A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

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A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC) ◽

10.1109/asscc.2015.7387463 ◽

2015 ◽

Cited By ~ 4

Author(s):

Jianwei Liu ◽

Chi-Hang Chan ◽

Sai-Weng Sin ◽

U Seng-Pan ◽

Rui Paulo Martins

Keyword(s):

Time Domain ◽

Flash Adc

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A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.k1003.09811s19 ◽

2019 ◽

Vol 8 (11S) ◽

pp. 11-19

Keyword(s):

Comparative Analysis ◽

High Resolution ◽

Low Power ◽

Time Domain ◽

High Speed ◽

Sampling Rate ◽

Cmos Technology ◽

Digital Converter ◽

Flash Adc ◽

Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

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