A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350017 ◽  
Author(s):  
GUANZHONG HUANG ◽  
PINGFEN LIN
Keyword(s):  
Time Domain ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Sampling Rate ◽  
Digital Signal ◽  
Input Voltage ◽  
Gray Code ◽  
Digital Circuit ◽  
Cmos Process ◽  
Flash Adc

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

Implementation of Single-Phase Two-Switch Midpoint Unidirectional Multilevel Converter System

2018 ◽  
Vol 19 (4) ◽  
Author(s):  
Peethala Rajiv Roy ◽  
P. Parthiban ◽  
B. Chitti Babu
Keyword(s):  
Single Phase ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Input Voltage ◽  
Open Loop ◽  
Current Control ◽  
Control Technique ◽  
Control Scheme

Abstract This paper deals with implementation of a single-phase three level converter system under low voltage condition. The frequency of the switches is made constant and involves change in ${t_{on}}$ and ${t_{off}}$ duration. For this condition the pulse width modulation control scheme for a single phase three level rectifier is developed to improve the power quality. The hysteresis current control technique is adopted to bring forth three-level PWM on the dc side of the bridge rectifier and to achieve high power factor and low harmonic distortion. Based on the proposed control scheme, the line current is driven to follow the sinusoidal current command which is in phase with the supply voltage. By using three-level voltage pattern the blocking voltage of each power device is clamped to half of the dc link voltage. The simulation and experimental results of 20W converter under low input voltage condition are shown to verify the circuit performance. Open loop simulation and hardware tests are implemented by applying a low voltage of 15 V(rms) on the input side.

Design of a Digital Baseband Processor for UHF Tags

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2060
Author(s):  
Na Bai ◽  
Liang Wang ◽  
Yaohua Xu ◽  
Yi Wang
Keyword(s):  
Data Processing ◽  
Low Voltage ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Cmos Process ◽  
Front End ◽  
Rf Front End ◽  
Machine Module ◽  
Baseband Processor ◽  
Digital Baseband

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals High-Power Multimodular Matrix Converters and Modulation

2021 ◽  
Author(s):  
Jiacheng Wang
Keyword(s):  
High Power ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Input Voltage ◽  
Duty Ratio ◽  
Modulation Scheme ◽  
Switching Frequency ◽  
Space Vector ◽  
Phase Switching ◽  
Matrix Converters

High-power multimodular matrix converters (MMMCs) comprising multiple threephase to single-phase matrix converter modules have emerged as a viable topology candidate for medium-voltage adjustable speed drives. As a combination of direct power conversion and cascaded multilevel structure, the MMMCs inherit features such as elimination of dc capacitors, four quadrant operation capability, employment of lowvoltage devices only, and superior output waveform quality under a limited device switching frequency. Due to their particular topological structure, modulation scheme design for the MMMCs is not straightforward and complicated. The presented work is mainly focused on development of suitable modulation schemes for the MMMCs. Several viable schemes as well as their corresponding switching patterns are proposed and verified by both simulation and experimental results. In order for the MMMCs to produce sinusoidal waveforms at both input and output ac terminals, a direct transfer matrix based modulation scheme is presented. It is revealed that a suitable modulation strategy for the MMMCs should aim at fabricating the total input current on the primary side of the isolation transformer. For topologies with more than two modules in cascade on each output phase, switching period displacement is necessary among modules to generate multilevel output waveforms. An indirect space vector based modulation scheme for the MMMCs is developed. With a few presumptions satisfied and viewed from a certain perspective, the MMMCs can still be modeled indirectly and be divided into fictitious rectifier and inverter stages. Therefore, space vector modulation methods can be independently applied to both stages for duty ratio calculation, before the results are converted and combined for determining per-phase output pulses. A new output switching pattern providing improved harmonic performance is also proposed. A novel modulation scheme based on diode rectifier emulation and phase-shifted sinusoidal pulse-width modulation is proposed. The method sacrifices input power factor adjustment, but enables the use of an indirect module construction leading to significantly reduced device count and complexity. Strategy for reducing additional switchings caused by input voltage ripples is also implemented and explained. In addition to simulation verifications, all the proposed schemes are further tested experimentally on a low-voltage prototype built in the lab. Details about the prototype implementation are introduced.

A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger

2019 ◽  
Vol 29 (04) ◽  
pp. 2020002
Author(s):  
Yasin Bastan ◽  
Parviz Amiri
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Design Procedure ◽  
Schmitt Trigger ◽  
Input Voltage ◽  
Cmos Process ◽  
Differential Mode ◽  
Digital Cmos ◽  
Hysteresis Width ◽  
Chip Area

A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[Formula: see text]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. The proposed circuit occupies only [Formula: see text][Formula: see text][Formula: see text]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[Formula: see text]mV and consumes only 6.64[Formula: see text]nW power.

scholarly journals A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

2019 ◽  
Vol 8 (11S) ◽  
pp. 11-19
Keyword(s):  
Comparative Analysis ◽  
High Resolution ◽  
Low Power ◽  
Time Domain ◽  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

A Review of Start-Up Circuits for Low Voltage Self-Powered DC-Type Energy Harvesters

2016 ◽  
Vol 25 (07) ◽  
pp. 1630003 ◽  
Author(s):  
Chuang Wang ◽  
Zunchao Li
Keyword(s):  
Direct Current ◽  
Lower Cost ◽  
Low Voltage ◽  
Input Voltage ◽  
Cmos Process ◽  
General Classification ◽  
Low Input ◽  
Energy Harvesters ◽  
Start Up ◽  
Self Powered

Various start-up circuits (SUCs) for low input voltage self-powered direct current-type (DC-type) energy harvesters have been proposed in recent years, and their structures have been evolving and changing continuously. A general classification and systematic overview of SUCs are presented here. With the development of CMOS process technologies, recent advances in SUCs have paved the way for lower input voltage, simpler structures, lower cost, and better performance. So far, no works have given an overall description of SUCs for low input voltage self-powered energy harvesters. This work is intended to not only provide insights into the topologies of SUCs, but also make a conclusion which identifies their developing tendency.

scholarly journals Mismatch Insensitive Voltage Level Shifter Based on Two Feedback Loops

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1391
Author(s):  
Zushuai Xie ◽  
Zhiqiang Wu ◽  
Jianhui Wu
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Propagation Delay ◽  
Feedback Loops ◽  
Normal Operation ◽  
Level Shift ◽  
Cmos Process ◽  
Voltage Level ◽  
Level Shifter ◽  
Voltage Conversion

This paper presents a voltage level shifter (VLS) based on two feedback loops. The complementary feedback signals in the high voltage domain are re-used to assist voltage conversion and the complementary phase in the low voltage domain is not required. Unlike the conventional VLS, which depends on the pull-up network and pull-down network to achieve level shift, the transitions of both high-to-low and low-to-high of the proposed VLS are undertaken by two different feedback loops, respectively. Implemented in a standard 180 nm CMOS process, post-layout Monte Carlo (MC) simulations from 4000 points under mismatch variation show that the dynamic power (DP) and the propagation delay (PD) of the proposed VLS are 105.3 nW and 2.0 ns, respectively, at an input voltage VIN = 0.4 V with input frequency fin = 0.1 MHz. Meanwhile, the excellent normalized standard deviation of DP and PD is obtained with the proposed scheme. The temperature range for normal operation is from −20 °C to 85 °C.

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