A novel test circuit for automatically detecting electrochemical migration and conductive anodic filament formation

1999 ◽  
Vol 28 (11) ◽  
pp. 1158-1163 ◽  
Author(s):  
W. Jud Ready ◽  
Laura J. Turbini ◽  
Roger Nickel ◽  
John Fischer
2008 ◽  
Vol 15 (1) ◽  
pp. 39-44 ◽  
Author(s):  
Antonio Caputo ◽  
Laura J. Turbini ◽  
Doug D. Perovic

2010 ◽  
Vol 2010 (1) ◽  
pp. 000829-000835
Author(s):  
Koushik Ramachandran ◽  
Fuhan Liu ◽  
Nitesh Kumbhat ◽  
Baik-Woo Lee ◽  
Venky Sundaram ◽  
...  

High I/O density and green materials are the two major drivers of package substrates for flip-chip and 3D IC packaging. Future organic laminate substrates will require 5–25 μm lines and spaces and through-package-via (TPV) pitch of 50–100 μm. This ultra fine pitch requirement will lead to serious substrate failures due to electrochemical migration and conductive anodic filament (CAF). Therefore, there is a need to develop new halogen-free materials and investigate their reliability in ultra-fine pitch applications. This work focuses on four areas, 1) Advanced halogen-free materials, 2) Surface insulation resistance (SIR) in fine lines and spaces, 3) Conductive anodic filament (CAF) in fine-pitch TPVs, and 4) Flip-chip interconnection reliability. The substrate materials selected for this study include resin formulations that incorporate halogen-free flame retardants onto the polymer backbone. The SIR was studied on substrates with 50 μm spaced copper traces and CAF was studied with TPVs of 150 μm and 400 μm spacing. In both the tests, the halogen-free substrates were observed to show better electrochemical migration resistance in comparison to brominated FR-4. Flip-chip reliability was studied by subjecting the test substrates to Thermal Cycling Test (TCT), Unbiased-Highly Accelerated Stress Test (U-HAST) and High Temperature Storage (HTS) test. Scanning Acoustic Microscopy (C-SAM) analysis and electrical resistance measurements were performed after each of the reliability tests. The test substrates passed 200 hours of HTS, 96 hours of HAST and 2000 cycles in TCT respectively. The flip-chip reliability results indicate that these materials have the potential for replacing the conventional halogenated substrates for high density packaging applications.


Author(s):  
Kristopher D. Staller ◽  
Corey Goodrich

Abstract Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.


Author(s):  
Daniel Nuez ◽  
Phoumra Tan

Abstract Conductive anodic filament (CAF) formation is a mechanism caused by an electrochemical migration of metals from a metal trace in ICs or in PCBs. This is commonly caused by the moisture build-up in the affected metal terminals in an IC package or PC board caused by critical temperature, high humidity and high voltage gradients conditions. This phenomenon is known to have caused catastrophic field failures on various OEMs electronic components in the past [1,7]. Most published articles on CAF described the formation of the filament in a lateral formation through the glass fiber interfaces between two adjacent metal planes [1-6, 8-12]. One common example is the CAF formation seen between PTH (Plated through Hole) in the laminated substrate with two different potentials causing shorts [1-6, 8-12]. In this paper, the Cu filament grows in a vertical fashion (z-axis formation) creating a vertical plane shorts between the upper and lower metal terminals in a laminated IC package substrate. The copper growth migration does not follow the fiber strands laterally or vertically through them. Instead, it grows through the stress created gaps between the impregnated carbon epoxy fillers from the upper metal trace to the lower metal trace with two different potentials, between the glass fibers. This vertical CAF mechanism creates a low resistive short that was sometimes found to be intermittent in nature. This paper presents some successful failure analysis approaches used to isolate and detect the failure locations for this type of failing devices. This paper also exposes the unique physical appearance of the vertical CAF formation.


Author(s):  
Anil Kurella ◽  
Aravind Munukutla ◽  
J.S. Lewis

Abstract PCB surface finishes like Immersion silver (ImAg) are commonly used in Pb-free manufacturing environments following RoHS legislation. With this transition, however the numbers of field failures associated with electrochemical migration, copper sulphide corrosion, via barrel galvanic corrosion are on a steady rise. More often than not ImAg surfaces seem to assist these failing signatures. As computers penetrate into emerging markets with humid and industrialized environments there is a greater concern on the reliability and functionality of these electronic components.


Author(s):  
Bhanu Sood ◽  
Michael Pecht

Abstract Failures in printed circuit boards account for a significant percentage of field returns in electronic products and systems. Conductive filament formation is an electrochemical process that requires the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. With the advent of lead-free initiatives, boards are being exposed to higher temperatures during lead-free solder processing. This can weaken the glass-fiber bonding, thus enhancing conductive filament formation. The effect of the inclusion of halogen-free flame retardants on conductive filament formation in printed circuit boards is also not completely understood. Previous studies, along with analysis and examinations conducted on printed circuit boards with failure sites that were due to conductive filament formation, have shown that the conductive path is typically formed along the delaminated fiber glass and epoxy resin interfaces. This paper is a result of a year-long study on the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style, and conductor spacing on times to failure due to conductive filament formation.


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