A low power time-to-digital converter for all-digital phase-locked loop

2011 ◽  
Vol 28 (3) ◽  
pp. 402-408 ◽  
Author(s):  
Guangming Yu ◽  
Yu Wang ◽  
Huazhong Yang
Keyword(s):  
Low Power ◽  
Phase Locked Loop ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Digital Phase

scholarly journals Semidigital PLL Design for Low-Cost Low-Power Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-9
Author(s):  
Ni Xu ◽  
Woogeun Rhee ◽  
Zhihua Wang
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detection ◽  
Linear Phase ◽  
Digital Converter ◽  
Clock Generation ◽  
Time To Digital Converter ◽  
Simulation Results

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

Low‐power, wide‐range time‐to‐digital converter for all digital phase‐locked loops

2013 ◽  
Vol 49 (2) ◽  
pp. 96-97 ◽  
Author(s):  
C.‐H. Jeong ◽  
C.‐K. Kwon ◽  
H. Kim ◽  
I.‐C. Hwang ◽  
S.‐W. Kim
Keyword(s):  
Low Power ◽  
Phase Locked Loops ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Digital Phase ◽  
Wide Range ◽  
Digital Phase Locked Loops

scholarly journals ALL DIGITAL PHASE-LOCKED LOOP / VISIŠKAI SKAITMENINĖ FAZĖS DERINIMO KILPA

2013 ◽  
Vol 5 (2) ◽  
pp. 128-132
Author(s):  
Marijan Jurgo
Keyword(s):  
Phase Locked Loop ◽  
Cmos Technology ◽  
Quantization Noise ◽  
Loop Structure ◽  
Digital Converter ◽  
Classical Structure ◽  
Time To Digital Converter ◽  
Digital Phase ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator

The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33 to −82.17 dBc/Hz, with tres = 8.64–27.71 ps, TSVG = 143–333 ps, FREF = 20–60 MHz. Article in Lithuanian. Santrauka Nagrinėjama fazės derinimo kilpa (FDK), jos veikimas, klasikinės struktūros FDK trūkumai nanometrinėse technologijose, galimi jų sprendimo būdai. Siūlomas perėjimas prie visiškai skaitmeninės fazės derinimo kilpos. Aprašomi pagrindiniai visiškai skaitmeninės FDK blokai – laikinis skaitmeninis keitiklis (LSK) ir skaitmeniniu būdu valdomas generatorius (SVG). Aptariamas LSK ir SVG atsirandantis kvantavimo triukšmas ir jo mažinimo priemonės. Apskaičiuota 65 nm KMOP technologijoje pasiekiama inverterio vėlinimo trukmė, lygi nuo 8,64 iki 27,71 ps, ir LSK triukšmo lygis, lygus nuo −104,33 iki −82,17 dBc/Hz, kai inverterio vėlinimo trukmė t res = 8,64–27,71 ps, SVG generuojamo signalo periodas TSVG = 143–333 ps, o atraminio signalo dažnis FREF = 20–60 MHz.

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