scholarly journals Semidigital PLL Design for Low-Cost Low-Power Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-9
Author(s):  
Ni Xu ◽  
Woogeun Rhee ◽  
Zhihua Wang
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detection ◽  
Linear Phase ◽  
Digital Converter ◽  
Clock Generation ◽  
Time To Digital Converter ◽  
Simulation Results

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching

2011 ◽  
Vol 58 (3) ◽  
pp. 169-173 ◽  
Author(s):  
Manho Kim ◽  
Hyunjoong Lee ◽  
Jong-Kwan Woo ◽  
Nan Xing ◽  
Min-Oh Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Time Stretching

scholarly journals ALL DIGITAL PHASE-LOCKED LOOP / VISIŠKAI SKAITMENINĖ FAZĖS DERINIMO KILPA

2013 ◽  
Vol 5 (2) ◽  
pp. 128-132
Author(s):  
Marijan Jurgo
Keyword(s):  
Phase Locked Loop ◽  
Cmos Technology ◽  
Quantization Noise ◽  
Loop Structure ◽  
Digital Converter ◽  
Classical Structure ◽  
Time To Digital Converter ◽  
Digital Phase ◽  
Digitally Controlled ◽  
Digitally Controlled Oscillator

The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33 to −82.17 dBc/Hz, with tres = 8.64–27.71 ps, TSVG = 143–333 ps, FREF = 20–60 MHz. Article in Lithuanian. Santrauka Nagrinėjama fazės derinimo kilpa (FDK), jos veikimas, klasikinės struktūros FDK trūkumai nanometrinėse technologijose, galimi jų sprendimo būdai. Siūlomas perėjimas prie visiškai skaitmeninės fazės derinimo kilpos. Aprašomi pagrindiniai visiškai skaitmeninės FDK blokai – laikinis skaitmeninis keitiklis (LSK) ir skaitmeniniu būdu valdomas generatorius (SVG). Aptariamas LSK ir SVG atsirandantis kvantavimo triukšmas ir jo mažinimo priemonės. Apskaičiuota 65 nm KMOP technologijoje pasiekiama inverterio vėlinimo trukmė, lygi nuo 8,64 iki 27,71 ps, ir LSK triukšmo lygis, lygus nuo −104,33 iki −82,17 dBc/Hz, kai inverterio vėlinimo trukmė t res = 8,64–27,71 ps, SVG generuojamo signalo periodas TSVG = 143–333 ps, o atraminio signalo dažnis FREF = 20–60 MHz.

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

2021 ◽  
Vol 16 (12) ◽  
pp. C12010
Author(s):  
L.A. Kadlubowski ◽  
P. Kmon
Keyword(s):  
Single Photon ◽  
Photon Counting ◽  
Cmos Technology ◽  
Time Of Arrival ◽  
Ring Oscillators ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Recording Channel ◽  
Simulation Results ◽  
28 Nm

Abstract The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

scholarly journals A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

2021 ◽  
pp. 1-1
Author(s):  
Wei Zhang ◽  
Hanhan Sun ◽  
Christopher Edwards ◽  
Datao Gong ◽  
Xing Huang ◽  
...  
Keyword(s):  
Low Power ◽  
Digital Converter ◽  
Time To Digital Converter
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