Evolution behavior of γ″ phase of IN718 superalloy in temperature/stress coupled field

Author(s):  
Han-zhong Deng ◽  
Lei Wang ◽  
Yang Liu ◽  
Xiu Song ◽  
Fan-qiang Meng ◽  
...  
2021 ◽  
pp. 111684
Author(s):  
Hanzhong Deng ◽  
Lei Wang ◽  
Yang Liu ◽  
Xiu Song ◽  
Fanqiang Meng ◽  
...  

2020 ◽  
Vol 53 (2) ◽  
Author(s):  
Khalil Ahmed Laghari ◽  
Abdul Jabbar Pirzada ◽  
Mahboob Ali Sial ◽  
Muhammad Athar Khan ◽  
Jamal Uddin Mangi

2020 ◽  
Vol 52 (5) ◽  
Author(s):  
De-Gong Wu ◽  
Qiu-Wen Zhan ◽  
Hai-Bing Yu ◽  
Bao-Hong Huang ◽  
Xin-Xin Cheng ◽  
...  

2018 ◽  
Author(s):  
Jungsuk Ko ◽  
Hoonchang yang ◽  
Hyungchae Jeon ◽  
Gyuyoung Nam ◽  
Youngseok Ryu ◽  
...  

Abstract The necessity of hot temperature stress is widely recognized as the initial stress methodology to maintain the stability of products from infant defects in device [1, 2]. However, hot temperature stress has a disadvantage in terms of stress uniformity because temperature variation according to stress environment such as chamber, board, and tester accelerates different stress effects per chips. In addition, this stress condition can cause serious reliability problem in the mass production environments. Therefore, the stress temperature should be lowered to minimize the temperature deviation due to the production environments. The reduction of stress temperature cause the lack of stress amount, so optimized stress voltage and time to maintain the stress condition is required. In this study, various stress voltage and time with decreasing temperature were evaluated in consideration of lifetime that unit elements such transistors and capacitors did not degrade by any stress conditions. In addition, it was confirmed that stress uniformity can be improved in the stress condition obtained by the evaluation. Furthermore, the enhanced initial failure screen ability was proven with mass evaluations.


Author(s):  
D-J Kim ◽  
I-G Kim ◽  
J-Y Noh ◽  
H-J Lee ◽  
S-H Park ◽  
...  

Abstract As DRAM technology extends into 12-inch diameter wafer processing, plasma-induced wafer charging is a serious problem in DRAM volume manufacture. There are currently no comprehensive reports on the potential impact of plasma damage on high density DRAM reliability. In this paper, the possible effects of floating potential at the source/drain junction of cell transistor during high-field charge injection are reported, and regarded as high-priority issues to further understand charging damage during the metal pad etching. The degradation of block edge dynamic retention time during high temperature stress, not consistent with typical reliability degradation model, is analyzed. Additionally, in order to meet the satisfactory reliability level in volume manufacture of high density DRAM technology, the paper provides the guidelines with respect to plasma damage. Unlike conventional model as gate antenna effect, the cell junction damage by the exposure of dummy BL pad to plasma, was revealed as root cause.


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