Mechanism Analysis of Dynamic On-State Resistance Degradation for a Commercial GaN HEMT Using Double Pulse Test

The dynamic on-resistance (RON) behavior of one commercial GaN HEMT device with p-GaN gate is investigated under hard-switching conditions. The non-monotonic performance of dynamic RON with off-state voltage ranging from 50 to 400 V is ascribed to the “leaky dielectric” model. The highest normalized RON value of 1.22 appears at 150 and 200 V. The gradual increase and following maximum of dynamic RON are found when the device is exposed to a stress voltage for an extended stress time under 100 and 200 V, which is due to a much longer trapping time compared to detrapping time related to deep acceptors and donors. No obvious RON degradation, thanks to the suppressed trapping effect, is observed at higher VDS. From the multi-pulse test, the dynamic RON is seen to be insensitive to the frequency. It is demonstrated that the leakage, especially under source and drain contact, is a key issue in the dynamic resistance degradation.

Modeling of Threshold Voltage Hysteresis in SiC MOSFET Device

In this paper, we report on the simulation results of instability threshold voltage of SiC MOSFET device. Hysteresis cycles of threshold voltage suggest that trapping and detrapping phenomena of electrons from the SiC layer into the oxide traps occur. Experiment suggests that positive threshold voltage shifts (ΔVth) caused by a positive stress voltage to the gate, are almost fully recovered by applying negative stress voltage. This work assumes uniform trap densities extending from SiC interface at a limited depth into oxide.