A breakdown voltage model for implanted resurf p-LDMOS device on n+ buried layer

In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakdown voltage increased by approximately 30% compared with conventional NPT-TIGBT.

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Novel 4H‐SiC BJT utilizing floating buried layer in base for high current gain, high current gain stability and high breakdown voltage

COMPEL The International Journal for Computation and Mathematics in Electrical and Electronic Engineering ◽

10.1108/03321641011014977 ◽

2010 ◽

Vol 29 (2) ◽

pp. 515-521

Author(s):

Yourun Zhang ◽

Bo Zhang ◽

Zhaoji Li ◽

Xiaochuan Deng ◽

Xilin Liu

Keyword(s):

Breakdown Voltage ◽

Current Gain ◽

High Current ◽

High Breakdown Voltage ◽

Buried Layer

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A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

Solid-State Electronics ◽

10.1016/j.sse.2007.01.034 ◽

2007 ◽

Vol 51 (3) ◽

pp. 493-499 ◽

Cited By ~ 71

Author(s):

Xiaorong Luo ◽

Bo Zhang ◽

Zhaoji Li

Keyword(s):

Electric Field ◽

Analytical Model ◽

Breakdown Voltage ◽

High Voltage ◽

Buried Layer

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Increasing breakdown voltage of LDMOST using buried layer

Journal of Electronics (China) ◽

10.1007/s11767-003-0083-x ◽

2003 ◽

Vol 20 (1) ◽

pp. 29-32

Author(s):

Lei Han ◽

Xingning Ye ◽

Xingbi Chen

Keyword(s):

Breakdown Voltage ◽

Buried Layer

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Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

Chinese Physics Letters ◽

10.1088/0256-307x/26/1/017303 ◽

2009 ◽

Vol 26 (1) ◽

pp. 017303 ◽

Cited By ~ 1

Author(s):

Ho Chi-Hon ◽

Liao Chien-Nan ◽

Chien Feng-Tso ◽

Tsai Yao-Tsung

Keyword(s):

Breakdown Voltage ◽

Silicon On Insulator ◽

Gate Bias ◽

Bias Effect ◽

Back Gate ◽

Optimizing Design ◽

Buried Layer

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Potential study of the enhanced breakdown voltage GaN MISFET based on partial AlN buried layer

Superlattices and Microstructures ◽

10.1016/j.spmi.2017.12.051 ◽

2018 ◽

Vol 114 ◽

pp. 314-320 ◽

Cited By ~ 4

Author(s):

Xin-Xing Fei ◽

Ying Wang ◽

Xin Luo ◽

Fei Cao ◽

Cheng-Hao Yu

Keyword(s):

Breakdown Voltage ◽

Potential Study ◽

Buried Layer

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Use N+ Buried Layer to Design a Low On-Resistance VDMOS

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.756-759.4267 ◽

2013 ◽

Vol 756-759 ◽

pp. 4267-4270

Author(s):

Zhao Huan Tang ◽

Bin Wang ◽

Jia Nan Wang ◽

Kai Zhou Tan

Keyword(s):

Breakdown Voltage ◽

High Voltage ◽

The Novel ◽

Novel Structure ◽

Buried Layer ◽

Buried Layers ◽

Resistance Value

A novel structure of a VDMOS in reducing on-resistance is proposed and experimentally demonstrated with a 200V N-channel VDMOS. With this structure, the on-resistance value of the VDMOS is reduced by 19.6% than that of a traditional VDMOS structure as the breakdown voltage almost maintained the same value, and there is only one additional mask in processing this new structure VDMOS, which is easily fabricated. By TCAD tool, the specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in high-voltage VDMOS and BCD areas.

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