Design and analysis of radiation-tolerant high frequency voltage controlled oscillator for PLL applications

2021 ◽  
Vol 131 ◽  
pp. 153543
Author(s):  
Prithiviraj Rajalingam ◽  
Selvakumar Jayakumar ◽  
Soumyaranjan Routray
Keyword(s):  
High Frequency ◽  
Voltage Controlled Oscillator ◽  
Radiation Tolerant

scholarly journals Magneto-Impedance Sensor Driven by 400 MHz Logarithmic Amplifier

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 355 ◽  
Author(s):  
Tomoo Nakai
Keyword(s):  
Thin Film ◽  
High Frequency ◽  
High Sensitivity ◽  
Smart Manufacturing ◽  
Voltage Controlled Oscillator ◽  
High Frequency Signal ◽  
Logarithmic Amplifier ◽  
Impedance Variation ◽  
Voltage Signal ◽  
Impedance Sensor

A thin-film magnetic field sensor is useful for detecting foreign matters and nanoparticles included in industrial and medical products. It can detect a small piece of tool steel chipping or breakage inside the products nondestructively. An inspection of all items in the manufacturing process is desirable for the smart manufacturing system. This report provides an impressive candidate for realizing this target. A thin-film magneto-impedance sensor has an extremely high sensitivity, especially, it is driven by alternatiing current (AC) around 500 MHz. For driving the sensor in such high frequency, a special circuit is needed for detecting an impedance variation of the sensor. In this paper, a logarithmic amplifier for detecting a signal level of 400 MHz output of the sensor is proposed. The logarithmic amplifier is almost 5 mm × 5 mm size small IC-chip which is widely used in wireless devices such as cell phones for detecting high-frequency signal level. The merit of the amplifier is that it can translate hundreds of MHz signal to a direct current (DC) voltage signal which is proportional to the radio frequency (RF)signal by only one IC-chip, so that the combination of a chip Voltage Controlled Oscillator (VCO), a magneto-impedance (MI) sensor and the logarithmic amplifier can compose a simple sensor driving circuit.

scholarly journals Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

2018 ◽  
Vol 7 (3.12) ◽  
pp. 871
Author(s):  
Thejusraj. H ◽  
Prithivi Raj ◽  
J Selvakumar ◽  
S Praveen Kumar
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
High Speed ◽  
Phase Locked Loop ◽  
Clock Recovery ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Voltage Controlled Oscillators ◽  
Clock Generation ◽  
Consumption Values

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

scholarly journals Design and Implementation of High Frequency and Low-Power Phase-locked Loop

2021 ◽  
Vol 7 (4) ◽  
pp. 70-86
Author(s):  
Premananda B. S. ◽  
Dhanush T. N. ◽  
Vaishnavi S. Parashar ◽  
D. Aneesh Bharadwaj
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
Supply Voltage ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Switching Rate ◽  
Loop Filter ◽  
Capture Range ◽  
Frequency Detector ◽  
Reduced Power Consumption

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process

2019 ◽  
Vol 11 (01) ◽  
pp. 63-70
Author(s):  
Deepak Balodi ◽  
Rahul Misra
Keyword(s):  
Metal Oxide ◽  
Power Consumption ◽  
Low Power ◽  
High Frequency ◽  
Cmos Technology ◽  
Phase Lock Loop ◽  
Voltage Controlled Oscillator ◽  
Phase Lock ◽  
Differential Pair ◽  
L Band

The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.

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