scholarly journals Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

2018 ◽  
Vol 7 (3.12) ◽  
pp. 871
Author(s):  
Thejusraj. H ◽  
Prithivi Raj ◽  
J Selvakumar ◽  
S Praveen Kumar
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
High Speed ◽  
Phase Locked Loop ◽  
Clock Recovery ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Voltage Controlled Oscillators ◽  
Clock Generation ◽  
Consumption Values

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

scholarly journals Design and Implementation of High Frequency and Low-Power Phase-locked Loop

2021 ◽  
Vol 7 (4) ◽  
pp. 70-86
Author(s):  
Premananda B. S. ◽  
Dhanush T. N. ◽  
Vaishnavi S. Parashar ◽  
D. Aneesh Bharadwaj
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
Supply Voltage ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Switching Rate ◽  
Loop Filter ◽  
Capture Range ◽  
Frequency Detector ◽  
Reduced Power Consumption

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

Low Voltage and High Oscillation Frequency Gated Ring Oscillator Using Bootstrap Technique

2013 ◽  
Vol 596 ◽  
pp. 195-198
Author(s):  
Nobukazu Takai ◽  
Ken Murakami ◽  
Haruo Kobayashi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Frequency ◽  
Oscillation Frequency ◽  
Low Voltage ◽  
Ring Oscillator ◽  
Low Power Consumption ◽  
High Oscillation ◽  
High Oscillation Frequency ◽  
Boot Strap

In this paper, a high frequency ring oscillator with low power consumption is proposed.The proposed ring oscillator is based on GRO by applying boot strap technique. Simulation resultsindicate that the FoM(Power Consumption/Oscillation Frequency) of the proposed ring oscillator isless than that of the conventional ring oscillator.

scholarly journals Power Efficient, Low Noise 2-5 GHz Phase Locked Loop

2011 ◽  
Vol 16 (4) ◽  
pp. 66-72
Author(s):  
V.Sh. Melikyan ◽  
A.A. Durgaryan ◽  
H.P. Petrosyan ◽  
A.G. Stepanyan
Keyword(s):  
Power Consumption ◽  
Efficient Solution ◽  
Phase Locked Loop ◽  
Low Noise ◽  
System Level ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Area Overhead ◽  
Output Noise ◽  
5 Ghz

A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead

scholarly journals A New Phase-Locked Loop with Active Inductor Ring Oscillator

2021 ◽  
Author(s):  
Mohamad El-Hage
Keyword(s):  
Phase Noise ◽  
High Speed ◽  
Low Voltage ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Timing Jitter ◽  
Ring Oscillator ◽  
Control Voltage ◽  
Active Inductor ◽  
Switching Noise

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

scholarly journals Non-Linear Mathematical Modelling for Phase Locked Loop

2018 ◽  
Vol 7 (4.10) ◽  
pp. 81
Author(s):  
Prithiviraj R ◽  
Selvakumar J
Keyword(s):  
High Speed ◽  
Linear Models ◽  
Low Cost ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Non Linear

Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.  

scholarly journals Memristor-Based Loop Filter Design for Phase Locked Loop

2019 ◽  
Vol 9 (3) ◽  
pp. 24 ◽  
Author(s):  
Naheem Olakunle Adesina ◽  
Ashok Srivastava
Keyword(s):  
Power Consumption ◽  
Filter Design ◽  
High Reliability ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Silicon Area ◽  
Main Challenge ◽  
A Charge ◽  
Basic Features

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.

scholarly journals CMOS ring oscillator delay cell performance: a comparative study

2019 ◽  
Vol 9 (3) ◽  
pp. 1757 ◽  
Author(s):  
D. A. Hadi ◽  
A. Z. Jidin ◽  
N. Ab Wahab ◽  
Madiha Z. ◽  
Nurliyana Abd Mutalib ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Power Consumption ◽  
Cell Performance ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Frequency Range ◽  
Differential Delay ◽  
Delay Cell ◽  
Current Follower ◽  
Last Stage

A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.

scholarly journals A New Phase-Locked Loop with Active Inductor Ring Oscillator

2021 ◽  
Author(s):  
Mohamad El-Hage
Keyword(s):  
Phase Noise ◽  
High Speed ◽  
Low Voltage ◽  
Building Blocks ◽  
Phase Locked Loop ◽  
Timing Jitter ◽  
Ring Oscillator ◽  
Control Voltage ◽  
Active Inductor ◽  
Switching Noise

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

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