A Fast-Transient low-dropout regulator (LDO) With Super Class-AB OTA

Author(s):  
Lanya Yu ◽  
Qisheng Zhang ◽  
Xiao Zhao ◽  
Boran Wen ◽  
Liyuan Dong ◽  
...  
2014 ◽  
Vol 543-547 ◽  
pp. 800-805 ◽  
Author(s):  
Shang Sheng Chi ◽  
Wei Hu ◽  
Ming Hui Fan ◽  
Yu Sen Xu ◽  
Guo Lin Chen

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.


2021 ◽  
Author(s):  
Darshil Patel

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.


2019 ◽  
Vol 19 (3) ◽  
pp. 254-259
Author(s):  
Jae-Hoon Jung ◽  
Jae-Hyung Jung ◽  
Young-Ho Jung ◽  
Hoe-Eung Jeong ◽  
Seong-Kwan Hong ◽  
...  

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