Fast Transient Fully Standard-Cell-Based All Digital Low-Dropout Regulator With 99.97% Current Efficiency

2018 ◽  
Vol 33 (9) ◽  
pp. 8011-8019 ◽  
Author(s):  
Muhammad Abrar Akram ◽  
Wook Hong ◽  
In-Chul Hwang
2021 ◽  
Author(s):  
Darshil Patel

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.


Author(s):  
Lanya Yu ◽  
Qisheng Zhang ◽  
Xiao Zhao ◽  
Boran Wen ◽  
Liyuan Dong ◽  
...  

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