scholarly journals Light-induced Recovery of Effective Carrier Lifetime in Boron-doped Czochralski Silicon at Room Temperature

2016 ◽  
Vol 92 ◽  
pp. 801-807 ◽  
Author(s):  
Hiroaki Ichikawa ◽  
Isao Takahashi ◽  
Noritaka Usami ◽  
Katsuhiko Shirasawa ◽  
Hidetaka Takato
2009 ◽  
Vol 156-158 ◽  
pp. 101-106 ◽  
Author(s):  
Douglas M. Jordan ◽  
Kanad Mallik ◽  
Robert J. Falster ◽  
Peter R. Wilshaw

The concept of fully encapsulated, semi-insulating silicon (SI-Si), Czochralski-silicon-on-insulator (CZ-SOI) substrates for silicon microwave devices is presented. Experimental results show that, using gold as a compensating impurity, a Si resistivity of order 400 kΩcm can be achieved at room temperature using lightly phosphorus doped substrates. This compares favourably with the maximum of ~180kΩcm previously achieved using lightly boron doped wafers and is due to a small asymmetry of the position of the two gold energy levels introduced into the band gap. Measurements of the temperature dependence of the resistivity of the semi-insulating material show that a resistivity ~5kΩcm can be achieved at 100°C. Thus the substrates are suitable for microwave devices working at normal operating temperatures and should allow Si to be used for much higher frequency microwave applications than currently possible.


2001 ◽  
Vol 90 (5) ◽  
pp. 2397-2404 ◽  
Author(s):  
S. W. Glunz ◽  
S. Rein ◽  
J. Y. Lee ◽  
W. Warta

Author(s):  
Abigail Rose Meyer ◽  
Craig P Taylor ◽  
Michael Venuti ◽  
Serena Eley ◽  
Vincenzo LaSalvia ◽  
...  

Boron-doped Czochralski (Cz) Si is the most commonly used semiconductor in the fabrication of solar cells. The minority carrier lifetime in boron-doped Cz Si decreases upon light exposure due to...


2020 ◽  
Vol 1004 ◽  
pp. 899-904
Author(s):  
Akihiro Koyama ◽  
Yuji Kiuchi ◽  
Tomonori Mizushima ◽  
Kensuke Takenaka ◽  
Shinichiro Matsunaga ◽  
...  

We demonstrate 20 kV-class 4H-SiC n-channel implantation and epitaxial (IE)-IGBTs having both low on-state voltage and high blocking characteristics. We fabricated n-IE-IGBTs on a (0001) silicon face with free-standing epitaxial layers. Effective carrier lifetime increased significantly from 0.9 μs to 9.6 μs by a lifetime enhancement process. We used the IE structure to suppress an increase of the surface p+-well concentration, reduce implantation damage at the p+-well, and reduce junction field effect transistor (JFET) region resistance by ion implantation as a counter doping. The n-IE-IGBT at 100 A/cm2 on-state voltage and specific differential on-resistance was 8.2 V and 36.9 mΩcm2, respectively, at room temperature with a 30 V gate voltage. The blocking voltage was 26.8 kV at 45.7 μA.


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