Synergistic improvement of device performance and bias stress stability of IGZO TFT via back-channel graded nitrogen doping

2021 ◽  
Vol 305 ◽  
pp. 130749
Author(s):  
Lei Shi ◽  
Jingfeng Wang ◽  
Yue Zhang
Keyword(s):  
Nitrogen Doping ◽  
Device Performance ◽  
Bias Stress ◽  
Igzo Tft

Stability Improvement of Nitrogen Doping on IGO TFTs under Positive Gate Bias Stress and Hysteresis Test

2019 ◽  
Vol 8 (7) ◽  
pp. Q3034-Q3040 ◽  
Author(s):  
Yen-Chi Cheng ◽  
Sheng-Po Chang ◽  
Shoou-Jinn Chang ◽  
Tien-Hung Cheng ◽  
Yen-Lin Tsai ◽  
...  
Keyword(s):  
Nitrogen Doping ◽  
Gate Bias ◽  
Bias Stress ◽  
Gate Bias Stress

56.2: Investigating the IGZO-TFT Performances Under Gate-bias Stress With and Without Light Illumination for 4k2k 65-inch Displays

2013 ◽  
Vol 44 (1) ◽  
pp. 775-778 ◽  
Author(s):  
Bo-Liang Yeh ◽  
Chun-Nan Lin ◽  
Hsien-Kai Tseng ◽  
Cheng-Chung Wu ◽  
Chao-Hung Huang ◽  
...  
Keyword(s):  
Light Illumination ◽  
Gate Bias ◽  
Bias Stress ◽  
Igzo Tft ◽  
Gate Bias Stress

scholarly journals Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Anand Subramaniam ◽  
Kurtis D. Cantley ◽  
Eric M. Vogel
Keyword(s):  
Supply Voltage ◽  
Logic Gate ◽  
Logic Gates ◽  
Nanocrystalline Silicon ◽  
Propagation Delay ◽  
Stable Operation ◽  
Device Performance ◽  
Ring Oscillators ◽  
Bias Stress ◽  
Stress Degradation

Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of <10 μs/stage. These are the fastest circuits formed out of nanocrystalline silicon TFTs to date. The effect of bias stress degradation of TFTs on oscillation frequency is also explored, and relatively stable operation is shown with supply voltages >5 V for several hours.

scholarly journals Optimizing the Properties of InGaZnOx Thin Film Transistors by Adjusting the Adsorbed Degree of Cs+ Ions

Materials ◽  
2019 ◽  
Vol 12 (14) ◽  
pp. 2300
Author(s):  
He Zhang ◽  
Yaogong Wang ◽  
Ruozheng Wang ◽  
Xiaoning Zhang ◽  
Chunliang Liu
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Carrier Mobility ◽  
Oxygen Vacancies ◽  
Immersion Method ◽  
Bias Stress ◽  
Cs Ions ◽  
Transfer Properties ◽  
Igzo Tft

To improve the performance of amorphous InGaZnOx (a-IGZO) thin film transistors (TFTs), in this thesis, Cs+ ions adsorbed IGZO (Cs-IGZO) films were prepared through a solution immersion method at low temperature. Under the modification of surface structure and oxygen vacancies concentrations of a-IGZO film, with the effective introduction of Cs+ ions into the surface of a-IGZO films, the transfer properties and stability of a-IGZO TFTs are greatly improved. Different parameters of Cs+ ion concentrations were investigated in our work. When the Cs+ ions concentration reached 2% mol/L, the optimized performance Cs-IGZO TFT was obtained, showing the carrier mobility of 18.7 cm2 V−1 s−1, the OFF current of 0.8 × 10−10 A, and the threshold voltage of 0.2 V, accompanied by the threshold voltage shifts of 1.3 V under positive bias stress for 5000 s.

scholarly journals Electrical Performance and Bias-Stress Stability of Amorphous InGaZnO Thin-Film Transistors with Buried-Channel Layers

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 779
Author(s):  
Ying Zhang ◽  
Haiting Xie ◽  
Chengyuan Dong
Keyword(s):  
Thin Film Transistors ◽  
Field Effect ◽  
Nitrogen Doping ◽  
Electrical Performance ◽  
Field Effect Mobility ◽  
Nitrogen Doped ◽  
Bias Stress ◽  
Channel Layer ◽  
Buried Channel ◽  
Amorphous Ingazno

To improve the electrical performance and bias-stress stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs), we fabricated and characterized buried-channel devices with multiple-stacked channel layers, i.e., a nitrogen-doped a-IGZO film (front-channel layer), a conventional a-IGZO film (buried-channel layer), and a nitrogen-doped a-IGZO film (back-channel layer). The larger field-effect mobility (5.8 cm2V−1s−1), the smaller subthreshold swing value (0.8 V/dec, and the better stability (smaller threshold voltage shifts during bias-stress and light illumination tests) were obtained for the buried-channel device relative to the conventional a-IGZO TFT. The specially designed channel-layer structure resulted in multiple conduction channels and hence large field-effect mobility. The in situ nitrogen-doping caused reductions in both the front-channel interface trap density and the density of deep states in the bulk channel layers, leading to a small subthreshold swing value. The better stability properties may be related to both the reduced trap states by nitrogen-doping and the passivation effect of the nitrogen-doped a-IGZO films at the device back channels.

Impact of the Low Temperature Gate Dielectrics on Device Performance and Bias-Stress Stabilities of a-IGZO Thin-Film Transistors

2015 ◽  
Vol 4 (8) ◽  
pp. N99-N102 ◽  
Author(s):  
Manoj Nag ◽  
Ajay Bhoolokam ◽  
Soeren Steudel ◽  
Jan Genoe ◽  
Guido Groeseneken ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Gate Dielectrics ◽  
Device Performance ◽  
Bias Stress

scholarly journals Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

2018 ◽  
Vol 13 (1) ◽  
Author(s):  
Jae-Moon Chung ◽  
Xiaokun Zhang ◽  
Fei Shang ◽  
Ji-Hoon Kim ◽  
Xiao-Lin Wang ◽  
...  
Keyword(s):  
Device Performance ◽  
Clean Interface ◽  
Igzo Tft

Degradation Model of a-IGZO TFT due to High Drain Bias Stress

2019 ◽  
Vol 8 (7) ◽  
pp. Q3242-Q3248 ◽  
Author(s):  
Kihwan Kim ◽  
Sangho Jeon ◽  
Hyunjun Lee ◽  
Miseon Seo ◽  
Hyunguk Cho ◽  
...  
Keyword(s):  
Degradation Model ◽  
Bias Stress ◽  
Drain Bias ◽  
Igzo Tft

Particle characterization of CVD tungsten metallization for 64 MBIT DRAM

1991 ◽  
Vol 49 ◽  
pp. 896-897
Author(s):  
Marylyn Bennett-Lilley ◽  
Thomas T.H. Fu ◽  
David D. Yin ◽  
R. Allen Bowling
Keyword(s):  
Chemical Vapor ◽  
Device Performance ◽  
Particle Characterization ◽  
Particle Generation ◽  
Tungsten Hexafluoride ◽  
Homogeneous Particle ◽  
Multiple Levels ◽  
Circuit Density ◽  
Sources Of Contamination

Chemical Vapor Deposition (CVD) tungsten metallization is used to increase VLSI device performance due to its low resistivity, and improved reliability over other metallization schemes. Because of its conformal nature as a blanket film, CVD-W has been adapted to multiple levels of metal which increases circuit density. It has been used to fabricate 16 MBIT DRAM technology in a manufacturing environment, and is the metallization for 64 MBIT DRAM technology currently under development. In this work, we investigate some sources of contamination. One possible source of contamination is impurities in the feed tungsten hexafluoride (WF6) gas. Another is particle generation from the various reactor components. Another generation source is homogeneous particle generation of particles from the WF6 gas itself. The purpose of this work is to investigate and analyze CVD-W process-generated particles, and establish a particle characterization methodology.

Sign in / Sign up

Export Citation Format

Share Document