scholarly journals Optimizing the Properties of InGaZnOx Thin Film Transistors by Adjusting the Adsorbed Degree of Cs+ Ions

Materials ◽  
2019 ◽  
Vol 12 (14) ◽  
pp. 2300
Author(s):  
He Zhang ◽  
Yaogong Wang ◽  
Ruozheng Wang ◽  
Xiaoning Zhang ◽  
Chunliang Liu
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Carrier Mobility ◽  
Oxygen Vacancies ◽  
Immersion Method ◽  
Bias Stress ◽  
Cs Ions ◽  
Transfer Properties ◽  
Igzo Tft

To improve the performance of amorphous InGaZnOx (a-IGZO) thin film transistors (TFTs), in this thesis, Cs+ ions adsorbed IGZO (Cs-IGZO) films were prepared through a solution immersion method at low temperature. Under the modification of surface structure and oxygen vacancies concentrations of a-IGZO film, with the effective introduction of Cs+ ions into the surface of a-IGZO films, the transfer properties and stability of a-IGZO TFTs are greatly improved. Different parameters of Cs+ ion concentrations were investigated in our work. When the Cs+ ions concentration reached 2% mol/L, the optimized performance Cs-IGZO TFT was obtained, showing the carrier mobility of 18.7 cm2 V−1 s−1, the OFF current of 0.8 × 10−10 A, and the threshold voltage of 0.2 V, accompanied by the threshold voltage shifts of 1.3 V under positive bias stress for 5000 s.

Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Bias Stress

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa
Keyword(s):  
Thin Film ◽  
Temperature Dependence ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
The Other ◽  
Time Dependent ◽  
Silicon Thin Film ◽  
Bias Stress

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.

scholarly journals Channel Defect Profiling and Passivation for ZnO Thin-Film Transistors

Nanomaterials ◽  
2020 ◽  
Vol 10 (6) ◽  
pp. 1186
Author(s):  
Soo Cheol Kang ◽  
So Young Kim ◽  
Sang Kyung Lee ◽  
Kiyung Kim ◽  
Billal Allouche ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Oxygen Vacancies ◽  
Drain Current ◽  
Vacuum Treatment ◽  
Trap Level ◽  
Zno Thin Film ◽  
Electrical Characteristics ◽  
Bias Stress ◽  
Trap Assisted Tunneling

The electrical characteristics of Zinc oxide (ZnO) thin-film transistors are analyzed to apprehend the effects of oxygen vacancies after vacuum treatment. The energy level of the oxygen vacancies was found to be located near the conduction band of ZnO, which contributed to the increase in drain current (ID) via trap-assisted tunneling when the gate voltage (VG) is lower than the specific voltage associated with the trap level. The oxygen vacancies were successfully passivated after the annealing of ZnO in oxygen ambient. We determined that the trap-induced Schottky barrier lowering reduced a drain barrier when the drain was subjected to negative bias stress. Consequentially, the field effect mobility increased from 8.5 m2 V−1·s−1 to 8.9 m2 V−1·s−1 and on-current increased by ~13%.

Local-Degradation-Induced Threshold Voltage Shift in Turned-OFF Amorphous InGaZnO Thin Film Transistors Under AC Drain Bias Stress

2015 ◽  
Vol 36 (6) ◽  
pp. 579-581 ◽  
Author(s):  
Jong In Kim ◽  
In-Tak Cho ◽  
Chan-Yong Jeong ◽  
Daeun Lee ◽  
Hyuck-In Kwon ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Stress ◽  
Drain Bias ◽  
Amorphous Ingazno

DC and AC Gate-Bias Stability of Nanocrystalline Silicon Thin-Film Transistors Made on Colorless Polyimide Foil Substrates

2011 ◽  
Vol 1321 ◽  
Author(s):  
I-Chung Chiu ◽  
I-Chun Cheng ◽  
Jian Z. Chen ◽  
Jung-Jie Huang ◽  
Yung-Pei Chen
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Nanocrystalline Silicon ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Stress ◽  
Mechanical Tensile ◽  
Gate Bias Stress

ABSTRACTStaggered bottom-gate hydrogenated nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) were demonstrated on flexible colorless polyimide substrates. The dc and ac bias-stress stability of these TFTs were investigated with and without mechanical tensile stress applied in parallel to the current flow direction. The findings indicate that the threshold voltage shift caused by an ac gate-bias stress was smaller compared to that caused by a dc gate-bias stress. Frequency dependence of threshold voltage shift was pronounced in the negative gate-bias stress experiments. Compared to TFTs under pure electrical gate-bias stressing, the stability of the nc-Si:H TFTs degrades further when the mechanical tensile strain is applied together with an electrical gate-bias stress.

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