Improvement of CISSe / CdS / ZnO Structure Performance by SCAPS-1D.

This manuscript presents an optimization of the performances of the CISSe/CdS/ZnO structure. 12 tests were performed for each layer on thickness, gap energy and temperature using SCAPC-1D. Numerical data were compiled with the open circuit voltage, the short circuit density, the fill factor and the efficiency. The results obtained are confirmed with the measurements illustrated in the literature. The analyses indicate a progressive improvement in the performance of the structure for each test; an efficiency of 28.8 % was recorded for the CISSe layer while 30.07 % as an efficiency for CdS and 31.47 % for the absorbent layer. On the other hand, an open circuit voltage does not exceed 1.37V for the whole structure.Thus, these results are satisfied and encouraged.

High Photo Switching Response of n-ZnO/i-MoS2/p-Si Heterojunction Solar Cell

In this research work, We investigate the enhancement of photo conversion efficiency from ZnO nanostructure and MoS2 switching mechanism of heterostructure solar cell.The carrier transport of MoS2 generating more electron-hole pairs in the MoS2/Si interface.The photo switching resistance of MoS2 active layer that increasing in short circuit density to 40.9964[mA/cm2], and the effective light trapping of ZnO nanostructure with optimized thickness of ZnO,MoS2 better thermal stability.The SRH heating and Joule heating are minimized by photoswitching characterstics.The Joule and SRH heating rate evaluated from stationary mode of study and the values in the magnitude order of 1013 W/m3 and 1012 W/m3 The use of both ZnO and MoS2 nanostructure leads to total generation rate,charge carrier transport are improved.The photo conversion efficiency is achieved by 27.7364%

The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

MOSFET have been scaled down over the past few years in order to give rise to high circuit density and increase the speed of circuit. But scaling of MOSFET leads to issues such as poor control gate over the current which depends on gate voltage. Many short channel effects (SCE) influence the circuit performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by using multiple gates and by offering better control gate the device parameters. In Single gate MOSFET, gate electric field decreases but multigate MOSFET or FinFET provides better control over drain current. In this paper, different FET structures such as MOSFET, TFET and FINFET are designed at 22nm channel length and effect of doping had been evaluated and studied. To evaluate the performance donor concentration is kept constant and acceptor concentration is varied.

Improved Inkjet-Printed Pattern Fidelity: Suppressing Bulges by Segmented and Symmetric Drop Placement

Inkjet printing is a promising technique for printed micro-electronics due to low cost, customizability and compatibility with large-area, flexible substrates. However, printed line shapes can suffer from bulges at the start of lines and at corner points in 2D line patterns. The printed pattern can be multiple times wider than the designed linewidth. This can severely impact manufacturing accuracy and achievable circuit density. Bulging can be difficult to prevent without changing the ink-substrate-system, the drying conditions or the circuit design, all of which can be undesirable. Here, we demonstrate a novel printing methodology that solves this issue by changing the order in which drops are placed on the substrate. The pattern is split up into segments of three drops where the central drop is printed last. This symmetric printing prevents the unwanted ink flow that causes bulging. Larger bulge-free patterns are created by successively connecting segments. Line formation in both traditional linear printing and our novel segmented and symmetric printing was analyzed to understand and optimize results. The printing of X-, T-, and L-shapes is considerably improved compared with the traditional linear printing methodology.

Cost-effective thiophene-assisted novel dopant-free hole transport materials for efficient perovskite solar cell performance

Cost-effective, novel dopant-free hole transport material-assisted perovskite solar cells exhibit a champion short-circuit density 25.73 mA cm−2 and power conversion efficiency of 17.60%.

High-efficiency organic solar cells enabled by halogenation of polymers based on 2D conjugated benzobis(thiazole)

A novel polymer based on 2D conjugated benzobis(thiazole) exhibits a high power conversion efficiency of 14.8% in an organic solar cell with IT-4F as the acceptor, with short circuit density and open circuit voltage well-balanced therein.

Flexible PET Substrate for High-Definition Printing of Polymer Thick-Film Conductive Pastes

A major obstacle in screen printing conductive low-temperature curing polymer thick-film (PTF) pastes onto common flexible PET substrate materials is the substantial spread of the pastes beyond the designed line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This phenomenon prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other more involved and higher cost patterning methods. In many cases, flexible circuit fabricators, desiring more accurate high-definition circuit elements, may have to subcontract parts out of house to incorporate alternate patterning methods. This subcontracting, in turn, leads to a loss of control of both cost and lead time. This article will provide results of numerous in-house and field testings, comparing printed line width control, edge definition, and improved conductivity of printed polymer Ag conductors on different flexible PET substrates.

Flexible PET Substrate for High Definition Printing of Polymer Thick Film Conductive Pastes

A major obstacle in screen printing conductive low temperature curing polymer thick film (PTF) pastes onto common flexible PET substrate materials is the substantial spread of the pastes beyond the designed line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This phenomenon prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other, more involved and higher cost patterning methods. In many cases, flexible circuit fabricators, desiring more accurate high definition circuit elements, may have to subcontract parts out of house in order to incorporate alternate patterning methods. In-turn this subcontracting leads to a loss of control of both cost and lead time. This paper will provide results of numerous in-house and field testing, comparing printed line width control, edge definition, and improved conductivity of printed polymer Ag conductors on different flexible PET substrates.

Combining Fine Line Photoimageable with Multi-Step Thick Film for Improved Circuit Density

There is a strong market need for further miniaturization of microelectronic ceramic-based products; electronic components require an increasingly finer pitch interconnect. Screen-printing resolution is a limiting factor in further miniaturization of classical thick film. Photo imageable thick film technology (PITF) was proposed decades ago as a successor technology to thick film, to achieve finer pitch patterns. However, where classical multilayer thick film provides good routing and interconnect capabilities, but insufficient fine line resolution, PITF does the reverse: no multilayer routing but advanced fine line performance. A combination of PITF for fine pitch mounting with advanced MLTF for efficient routing has been developed, targeting a linewidth of 50 μm line/spaces and below. Test and demo panels were made, using combinations of PITF pastes and conventional screen-print materials. Results, process performance, and limiting factors are discussed.

Advanced Failure Analysis of Junction Profile Defect by Using EBAC/EBIC

As semiconductor device geometries shrink due to process technology development and circuit density rapidly increases, it is becoming extremely difficult to effectively analyze defects. Against this background, more precise and efficient techniques to analyze the root cause of defects is in constant demand. This paper proposes a method to quickly and accurately identify the true cause of device failure by using a nano probe EBAC/EBIC analysis technique. The most significant benefit of the EBAC/EBIC analysis technique is the ability to identify normal or abnormal circuit behavior with an intuitive image. This benefit can minimize the damage to a sample during the initial analysis phase, which has been an issue in the analysis of existing physical properties of semiconductors. In this paper, we identified the root cause of a series transistor defect in CIS (CMOS Image Sensor) product by using EBAC/EBIC (analysis) technique, and verified this with the assistance of SSRM (Scanning Spreading Resistance Microscopy) and APT (Atomic Probe Tomography). By doing so, we confirmed that the analysis technique proposed in this paper is very effective in identifying and pinpointing the true cause and location of the defect.