FPGA Implementation Of Dynamic Power, Area Optimized Reversible ALU For Various DSP Applications

In this paper we present two architectures for image segmentation using Sobel Operators. The first architecture is designed for optimum speed whereas the second one is designed for low power. To improve the speed of operation and to reduce the memory access two identical processing units operate parallelly. The first architecture is able to segment up to 800 images each of 640 × 480 pixels in one second at 500 MHz clock frequency consuming 27.31 mW dynamic power. The second architecture is able to segment up to 488 images each of 640 × 480 pixels in one second at 300 MHz clock frequency consuming 13.6 mW dynamic power.

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Low Power 32-Bit Floating Point Adder/Subtractor Design using 50nm CMOS VLSI Technology

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.j8788.0881019 ◽

2019 ◽

Vol 8 (10) ◽

pp. 662-674

Keyword(s):

Power Consumption ◽

Low Power ◽

Critical Path ◽

Experimental Results ◽

Floating Point ◽

Dynamic Power ◽

Custom Design ◽

Vlsi Technology ◽

Cmos Vlsi ◽

Dsp Applications

In many DSP applications, generally multipliers and adders are two key components which are highly complex and consume more power. Out of that the design of adder circuitry is quite complex compared to multiplier which consumes more power. Hence optimization of power consumption of adder circuits is a challenging task in the recent year and is a need of today’s world. In order to give a justice to this problem, work presented in this paper describes the technique of designing floating point adder and subtractor using low power pipelining technique which leads to a reduction in power consumption by a significant amount. Moreover, the presented work in the paper deals with the design of low power transistorized architecture for 32-bit floating point adder/ subtractor without and with pipelining approach in 50nm CMOS VLSI technology. The experimental results demonstrated that, the dynamic power consumption of the floating point adder/subtractor architectures is reduced significantly by employing pipelining technique as compared to the without pipelining technique. Also, in this work a significant improvement has been achieved in the critical path for pipelined approach compared to without pipeline approach. The proposed design is a full custom design prepared and analyzed using cadence 6.15 tool

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FPGA Implementation of Efficient FIR Filter

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.c6349.029320 ◽

2020 ◽

Vol 9 (3) ◽

pp. 3410-3412

Keyword(s):

Programming Language ◽

Filter Design ◽

Fir Filter ◽

Fpga Implementation ◽

Floating Point ◽

Matlab Software ◽

Dynamic Power ◽

Main Target ◽

Filter Operation ◽

Fir Filter Design

Improve the functionality of an FIR Filter by modifying the internal components used to design a filter. These past years have seen some great improvements in the speed, power, and area of the filter. Here, we will, therefore, use an ALU-based algorithm to design our FIR filter. The internal components of the ALU block will be an Adder and a Multiplier. A Floating point Adder and a Floating Point Multiplier will be the basic backbone of the ALU block, which finally will be used to design and implement our FIR filter design. Therefore, the parameters of the area are our main target but we will also see the power consumed by the Filter operation, both static and dynamic power consumed will be seen. The programming language will be written in VERILOG and the simulation and implementation of the design will be done by the help of Xilinx ISE suite version. One important aspect is that there will be 16 input samples and 16 coefficients which will be directly from a 16 tap filter. These coefficients and input values will be generated through MATLAB software.

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