scholarly journals Low Power 32-Bit Floating Point Adder/Subtractor Design using 50nm CMOS VLSI Technology

2019 ◽  
Vol 8 (10) ◽  
pp. 662-674
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Critical Path ◽  
Experimental Results ◽  
Floating Point ◽  
Dynamic Power ◽  
Custom Design ◽  
Vlsi Technology ◽  
Cmos Vlsi ◽  
Dsp Applications

In many DSP applications, generally multipliers and adders are two key components which are highly complex and consume more power. Out of that the design of adder circuitry is quite complex compared to multiplier which consumes more power. Hence optimization of power consumption of adder circuits is a challenging task in the recent year and is a need of today’s world. In order to give a justice to this problem, work presented in this paper describes the technique of designing floating point adder and subtractor using low power pipelining technique which leads to a reduction in power consumption by a significant amount. Moreover, the presented work in the paper deals with the design of low power transistorized architecture for 32-bit floating point adder/ subtractor without and with pipelining approach in 50nm CMOS VLSI technology. The experimental results demonstrated that, the dynamic power consumption of the floating point adder/subtractor architectures is reduced significantly by employing pipelining technique as compared to the without pipelining technique. Also, in this work a significant improvement has been achieved in the critical path for pipelined approach compared to without pipeline approach. The proposed design is a full custom design prepared and analyzed using cadence 6.15 tool

scholarly journals Power Considerations in Banked CAMs: A Leakage Reduction Approach

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-7 ◽  
Author(s):  
Pedro Echeverría ◽  
José L. Ayala ◽  
Marisa López-Vallejo
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Leakage Power ◽  
Experimental Results ◽  
Search Process ◽  
Dynamic Power ◽  
Leakage Reduction ◽  
And Storage ◽  
Reduction Approach

The content-based access of CAMs makes them of great interest in lookup-based operations. However, the large amounts of parallel comparisons required cause an expensive cost in power dissipation. In this work, we present a novel banked precomputation-based architecture for low-power and storage-demanding applications where the reduction of both dynamic and leakage power consumption is addressed. Experimental results show that the proposed banked architecture reduces up to an 89% of dynamic power consumption during the search process while the leakage power consumption is also minimized up to a 91%.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals LUT Based Generalized Parallel Counters for State - of - art FPGAs

2017 ◽  
Vol 21 (1) ◽  
pp. 3
Author(s):  
Burhan Khurshid
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Critical Path ◽  
Experimental Results ◽  
Considerable Reduction ◽  
Prior Work ◽  
Dynamic Power ◽  
Look Up Table ◽  
State Of Art

Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized fast carry chains. The  resulting structures are purely combinational and cannot be efficiently pipelined to achieve the potential FPGA performance. In this paper, we take an alternate approach and try to eliminate the fast carry chain from the GPC structure. We present a heuristic that maps GPCs on FPGAS using only general LUT fabric. The resultant GPCs are then easily re-timed by placing registers at the fan-out nodes of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry chain from the GPC structure with the same LUT count in most of the cases. Experimental results using Xilinx Kintex-7 FPGAs show a considerable reduction in critical path and dynamic power dissipation with same area utilization in most of the cases.

The Research and Design of the Adaptive Pulse Demagnetizer

2012 ◽  
Vol 182-183 ◽  
pp. 427-430
Author(s):  
Li Feng Wei ◽  
Liang Cheng ◽  
Xing Man Yang
Keyword(s):  
Adaptive Control ◽  
Power Consumption ◽  
Low Power ◽  
Control Method ◽  
Experimental Results ◽  
Low Power Consumption ◽  
Reliable Operation ◽  
Charge Current ◽  
Long Life ◽  
Research And Design

A adaptive control method of the pulse demagnetizer was presented, Can adjust the strength of the charge current automatically according to the changes of the magnetic content to ensure the constant of the magnetic field.The experimental results have shown that it has the advantages of low power consumption, strong anti-interference capability, stable and reliable operation, long life and good demagnetizing effect, when compared to the conventional demagnetizers.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

scholarly journals Low noise low power readout circuit for soft X ray detection

2003 ◽  
Vol 1 (03) ◽  
Author(s):  
A. Cerdeira-Estrada ◽  
A. De Luca ◽  
A. Cuttin ◽  
R. Mutihac
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Theoretical Calculations ◽  
Silicon Detector ◽  
Low Noise ◽  
Experimental Results ◽  
X Rays ◽  
Readout Circuit ◽  
X Ray ◽  
Low Power Cmos

A new low power CMOS ASIC for the detection of X-rays was optimized for low power and low noise. Theoretical calculations and optimizations are presented and compared with experimental results. Noise as low as 120+25*Cin [pF] ENC rms was obtained including a silicon detector of 1.3 pF and 0.3nA of leakage. The power consumption is less than 100 W. Other circuit parameters are also shown.

scholarly journals IMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER

2015 ◽  
pp. 239-244
Author(s):  
SYAM KUMAR NAGENDLA ◽  
K. MIRANJI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Processing System ◽  
Digital Signal ◽  
Signal Processing System ◽  
Speed Performance ◽  
Power Delay Product ◽  
Dsp Systems

Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.

scholarly journals FIR Filter Design using Floating Point Column Bypassing Technique

2019 ◽  
Vol 8 (2S4) ◽  
pp. 409-413 ◽  
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Truncation Error ◽  
Filter Design ◽  
Fir Filter ◽  
Floating Point ◽  
Switching Activity ◽  
Software And Hardware ◽  
Fir Filter Design ◽  
Dsp Applications

This paper presents the design of floating point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in a FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software.

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