Deformation mechanism and its effect on electrical conductivity of ACF flip chip package under thermal cycling condition: An experimental study

2006 ◽  
Vol 46 (2-4) ◽  
pp. 589-599 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Suk-Jin Ham ◽  
Kyung-Wook Paik
2012 ◽  
Vol 52 (7) ◽  
pp. 1441-1444 ◽  
Author(s):  
Yunsung Kim ◽  
Hyelim Choi ◽  
Hyoungjoo Lee ◽  
Dongjun Shin ◽  
Jinhan Cho ◽  
...  

2007 ◽  
Vol 539-543 ◽  
pp. 368-373 ◽  
Author(s):  
Cheng Jin ◽  
Ji Tai Niu ◽  
Shi Yu He ◽  
Hong Bin Geng ◽  
G. Long

In this paper, the micro-damage mechanisms of 5A06 Al alloy weld joints have been studied under the condition of constant load and cyclic thermal load. The mechanical performance variation of the base material and its weld joint are analyzed and compared. Microstructure analysis reveals that the main damage mechanism in weld joints is the interior voids nucleation and growth. The voids distribution and evolution govern the damage process. Test results also show most fractures occur at HAZ near the welding fusion line. The development of these voids results in the performance deterioration of the weld joints under thermal cycling condition.


Author(s):  
Yoshihiko Kanda ◽  
Kunihiro Zama ◽  
Yoshiharu Kariya ◽  
Takao Mikami ◽  
Takaya Kobayashi ◽  
...  

The effect of viscoelasticity of underfill on the reliability analysis of flip-chip package by using FEA has been investigated in this study. The analytical result on thermal warpage of a package is different depending on whether the underfill is assumed to be elastic or viscoelastic. The difference is prominent in materials with low Tg, specifically during the cooling process. The viscoelastic effect of the underfill on the fatigue life of the solder bumps is also appears in materials with low Tg, and the predicted fatigue life of a package is about twice as short if the underfill is assumed to be elastic instead of viscoelastic. Thus, the differences in the assumption regarding the viscoelastic properties of the underfill affect the reliability analysis of the packages under thermal cycling condition using FEA.


2019 ◽  
Vol 141 (4) ◽  
Author(s):  
John H. Lau

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.


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