Modeling of Underfilled PBGA Assemblies Using Both Viscoelastic and Elastic Material Properties

In microelectronics packaging industry, polymer based materials are used extensively. These polymer materials show viscoelastic behavior when subject to time dependent loads or deformations. The viscoelastic behavior highly depends on both temperature and time. In many cases, these viscoelastic properties are often neglected due to saving computational cost or unavailability of full characterization of the viscoelastic properties. To make accurate predictions of packaging mechanical behavior and reliability, it is important to accurately characterize the viscoelastic behavior of mold compounds, underfill encapsulants, adhesives and other polymers used in electronic assemblies. After characterization, these parameters can be used as input material property data for finite element analysis (FEA) simulations. In this study, both frequency dependent dynamic mechanical analysis (DMA) measurements, and strain and temperature dependent stress relaxation experiments were performed on a typical underfill material in order to characterize its linear viscoelastic behavior. In both cases, a master curve was determined using the assumption of time-temperature equivalence, and Prony series expansions were utilized to model the underfill material relaxation behavior. After that, these viscoelastic underfill material parameters were used in finite element models of underfilled ball grid array packages (Ultra CSP) subjected to thermal cycling from −40 to 125 °C. Separate simulations were also performed using temperature dependent elastic properties for the underfill material. In both cases, the solder joint fatigue life was estimated, and the effects of using viscoelastic properties for the underfill in solder joint fatigue life simulation were investigated.

Flip Chip Underfill RF Characterization

To develop reliable high-speed packages, characterization of the underfill material used in the flip-chip process has become of greater importance. The underfill, typically an epoxy resin-based material, offers thermal and structural benefits for the integrated circuit (IC) on package. With so many inputs and outputs (IOs) in close proximity to one another, the integrated circuits on package can have unexpected signal and power integrity issues. Furthermore, chip packages can support signals only up to the frequency where noise coupling (e.g., crosstalk, switching noise, etc.) leads to the malfunctioning of the system. Vertical interconnects, such as vias and solder bumps, are major sources of noise coupling. Inserting ground references between every signal net is not practical. For the solder bumps, the noise coupling depends on the permittivity of the underfill material. Therefore, characterizing the permittivity of the underfill material helps in predicting signal and power integrity issues. Such liquid or semi-viscous materials are commonly characterized from a simple fringe capacitance model of an open-ended coaxial probe immersed in the material. The open-ended coaxial method, however, is not as accurate as resonator-based methods. There is a need for a methodology to accurately extract the permittivity of liquid or semi-viscous materials at high frequencies. The proposed method uses solid walled cavity resonators, where the resonator is filled with the underfill material and cured. Dielectric characterization is a complex process, where the physical characteristics of the cavities must be known or accurately measured. This includes the conductivity of the conductors, roughness of the conductors, the dimensions of the cavity, and the port pin locations. This paper discusses some of the challenges that are encountered when characterizing dielectrics with cavity resonators. This characterization methodology can also be used to characterize other materials of interest.

Experimental and Numerical Investigation of Underfill Materials on Thermal Cycle Fatigue of Second Level Solder Interconnects Under Mean Temperature Conditions

With the larger size of Ball Grid Array (BGA) solder joints, the available volume for underfilling is significantly increased. Although the size of the solder joints and package dimension governs the volume of underfill material, the larger 2nd level solder interconnects are more susceptible to thermal fatigue with certain underfills and thermal profiles. In this study, BGA packages were underfilled with two dedicated underfill materials and two soft materials used as conformal coatings and encapsulants in electronic products. Each of the selected materials was subjected to two thermal profiles, one with low mean temperature and a second with a high mean temperature. The variation in mean cyclic temperature demonstrates the influence of temperature dependent behavior of each underfill material on the loads solder joints experience in a BGA package. Material characterization was performed on the package and underfill materials and incorporated into finite element models. The influence of underfill material glass transition temperature (Tg) was found to be a critical factor on fatigue endurance of solder interconnects. Fatigue crack orientation within solder joints were found to be aligned with axial (normal) direction for BGAs with high CTE underfill materials. Simulations determined the magnitude of axial loading associated with each underfill material properties responsible for reducing fatigue life. The results developed in this paper reveal the factors associated with reduced fatigue endurance of certain underfill materials under temperature profiles with mean temperature conditions and contribute to the development of new criteria of underfill material selection for 2nd level interconnects.