Abstract
To develop reliable high-speed packages, characterization of the underfill material used in the flip-chip process has become of greater importance. The underfill, typically an epoxy resin-based material, offers thermal and structural benefits for the integrated circuit (IC) on package. With so many inputs and outputs (IOs) in close proximity to one another, the integrated circuits on package can have unexpected signal and power integrity issues.
Furthermore, chip packages can support signals only up to the frequency where noise coupling (e.g., crosstalk, switching noise, etc.) leads to the malfunctioning of the system. Vertical interconnects, such as vias and solder bumps, are major sources of noise coupling. Inserting ground references between every signal net is not practical. For the solder bumps, the noise coupling depends on the permittivity of the underfill material. Therefore, characterizing the permittivity of the underfill material helps in predicting signal and power integrity issues.
Such liquid or semi-viscous materials are commonly characterized from a simple fringe capacitance model of an open-ended coaxial probe immersed in the material. The open-ended coaxial method, however, is not as accurate as resonator-based methods. There is a need for a methodology to accurately extract the permittivity of liquid or semi-viscous materials at high frequencies. The proposed method uses solid walled cavity resonators, where the resonator is filled with the underfill material and cured.
Dielectric characterization is a complex process, where the physical characteristics of the cavities must be known or accurately measured. This includes the conductivity of the conductors, roughness of the conductors, the dimensions of the cavity, and the port pin locations. This paper discusses some of the challenges that are encountered when characterizing dielectrics with cavity resonators. This characterization methodology can also be used to characterize other materials of interest.
