Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65nm technology platform

Microelectronics Reliability ◽

10.1016/j.microrel.2010.07.028 ◽

2010 ◽

Vol 50 (9-11) ◽

pp. 1373-1378

Author(s):

A. Tazzoli ◽

M. Cordoni ◽

P. Colombo ◽

C. Bergonzoni ◽

G. Meneghesso

Keyword(s):

Technology Platform ◽

Esd Protection ◽

Latch Up ◽

Protection Structures

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Pushing away the silicon limits of ESD protection structures: Exploration of crystallographic orientation

2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting ◽

10.1109/bipol.2008.4662743 ◽

2008 ◽

Author(s):

D. Tremouilles ◽

Yuan Gao ◽

M. Bafleur

Keyword(s):

Crystallographic Orientation ◽

Esd Protection ◽

Protection Structures

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Emitter injection control in LVTSCR for latch-up free ESD protection

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595) ◽

10.1109/miel.2002.1003363 ◽

2003 ◽

Author(s):

V. Vashchenko ◽

A. Concannon ◽

M. Ter Beek ◽

P. Hopper

Keyword(s):

Esd Protection ◽

Injection Control ◽

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Nano switching crossbar array ESD protection structures

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) ◽

10.1109/rfic.2013.6569612 ◽

2013 ◽

Author(s):

X. Wang ◽

Z. Shi ◽

J. Liu ◽

L. Wang ◽

R. Ma ◽

...

Keyword(s):

Crossbar Array ◽

Esd Protection ◽

Protection Structures

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Predictive device simulation for ESD protection structures validated with transient interferometric thermal-mapping experiments

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. ◽

10.1109/essder.2005.1546672 ◽

2005 ◽

Author(s):

S. Reggiani ◽

E. Gnani ◽

M. Rudan ◽

G. Baccarani ◽

S. Bychikhin ◽

...

Keyword(s):

Device Simulation ◽

Thermal Mapping ◽

Esd Protection ◽

Protection Structures

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3D electro-thermal modeling for ESD protection structures in Sub-100nm CMOS

2008 2nd IEEE International Nanoelectronics Conference ◽

10.1109/inec.2008.4585540 ◽

2008 ◽

Author(s):

L. Lin ◽

X. Wang ◽

J. Liu ◽

A. Wang ◽

H. Liu ◽

...

Keyword(s):

Thermal Modeling ◽

Esd Protection ◽

Protection Structures

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Optimization of on-chip ESD protection structures for RF operations

The 10th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications ◽

10.1109/edmo.2002.1174927 ◽

2003 ◽

Author(s):

J.J. Liou ◽

Xiaofang Gao ◽

J. Bernier ◽

G. Croft ◽

Waisum Wong ◽

...

Keyword(s):

Esd Protection ◽

On Chip ◽

Protection Structures

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Analysis of the LIGBT-based ESD Protection Circuit with Latch-up Immunity and High Robustness

Journal of the Korean Institute of Electrical and Electronic Material Engineers ◽

10.4313/jkem.2014.27.11.686 ◽

2014 ◽

Vol 27 (11) ◽

pp. 686-689

Author(s):

Jae Chang Kwak

Keyword(s):

Esd Protection ◽

Protection Circuit ◽

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Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection

Nanoscale Research Letters ◽

10.1186/s11671-019-3017-8 ◽

2019 ◽

Vol 14 (1) ◽

Author(s):

Zhuo Wang ◽

Zhao Qi ◽

Longfei Liang ◽

Ming Qiao ◽

Zhaoji Li ◽

...

Keyword(s):

Carrier Recombination ◽

Esd Protection ◽

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Latch-Up Immune Bi-Direction ESD Protection Clamp for Push-Pull RF Power Amplifier

IEICE Transactions on Electronics ◽

10.1587/transele.2019ecs6012 ◽

2020 ◽

Vol E103.C (4) ◽

pp. 194-196

Author(s):

Yibo JIANG ◽

Hui BI ◽

Wei ZHAO ◽

Chen SHI ◽

Xiaolei WANG

Keyword(s):

Power Amplifier ◽

Rf Power ◽

Rf Power Amplifier ◽

Esd Protection ◽

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Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.732-733.1207 ◽

2013 ◽

Vol 732-733 ◽

pp. 1207-1211

Author(s):

Shen Li Chen ◽

Tzung Shian Wu

Keyword(s):

Power Electronics ◽

High Voltage ◽

Power Device ◽

Esd Protection ◽

Buried Layer ◽

In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

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