Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

2013 ◽  
Vol 732-733 ◽  
pp. 1207-1211
Author(s):  
Shen Li Chen ◽  
Tzung Shian Wu
Keyword(s):  
Power Electronics ◽  
High Voltage ◽  
Power Device ◽  
Esd Protection ◽  
Buried Layer ◽  
Latch Up

In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

An Optimization Design in the HV nLDMOS by Taguchi Method

2012 ◽  
Vol 482-484 ◽  
pp. 81-84 ◽  
Author(s):  
Shen Li Chen ◽  
Tzung Shian Wu ◽  
Yun Ru Chen ◽  
Hung Wei Chen ◽  
Chun Hsing Shih ◽  
...  
Keyword(s):  
Taguchi Method ◽  
High Voltage ◽  
Optimization Design ◽  
Applied Model ◽  
Adaptive Adjustment ◽  
Buried Layer ◽  
The Times ◽  
Latch Up

This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L8(27). By this way, it can decrease the times of experiment much effectively.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

2001 ◽  
Author(s):  
Giho Cha ◽  
Youngchul Kim ◽  
Hyungwoo Jang ◽  
Hyunsoon Kang ◽  
Changsub Song
Keyword(s):  
High Voltage ◽  
Bipolar Transistors ◽  
Power Device ◽  
Insulated Gate Bipolar Transistors

scholarly journals Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology

2018 ◽  
Vol 201 ◽  
pp. 02004
Author(s):  
Shao-Ming Yang ◽  
Gene Sheu ◽  
Tzu Chieh Lee ◽  
Ting Yao Chien ◽  
Chieh Chih Wu ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
High Voltage ◽  
High Performance ◽  
Power Device ◽  
Simulation Tool ◽  
Process Technology ◽  
Surface Field ◽  
Kirk Effect ◽  
Tcad Simulation ◽  
Reduced Surface

High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.

ESD protection for high voltage LDMOS with sense FET

2002 ◽  
Author(s):  
Y.S. Choi ◽  
J.J. Kim ◽  
C.K. Jeon ◽  
M.H. Kim ◽  
S.L. Kim ◽  
...  
Keyword(s):  
High Voltage ◽  
Esd Protection

Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65nm technology platform

2010 ◽  
Vol 50 (9-11) ◽  
pp. 1373-1378
Author(s):  
A. Tazzoli ◽  
M. Cordoni ◽  
P. Colombo ◽  
C. Bergonzoni ◽  
G. Meneghesso
Keyword(s):  
Technology Platform ◽  
Esd Protection ◽  
Latch Up ◽  
Protection Structures
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