Emitter injection control in LVTSCR for latch-up free ESD protection

In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

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A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD protection

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual. ◽

10.1109/relphy.2003.1197728 ◽

2003 ◽

Cited By ~ 7

Author(s):

A. Concannon ◽

V.A. Vashchenko ◽

M. ter Beek ◽

P. Hopper

Keyword(s):

Negative Feedback ◽

Esd Protection ◽

Latch Up

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ESD protection Diode with Guard Ring Layout Optimized for Latch-up Immunity Enhancement in FinFET technology

2019 41st Annual EOS/ESD Symposium (EOS/ESD) ◽

10.23919/eos/esd.2019.8869972 ◽

2019 ◽

Author(s):

Kai-Ping Huang ◽

Po-Lin Peng ◽

Li-Wei Chu ◽

Yi-Feng Chang ◽

Tzu-Heng Chang ◽

...

Keyword(s):

Guard Ring ◽

Esd Protection ◽

Latch Up

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Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2004.833764 ◽

2004 ◽

Vol 39 (10) ◽

pp. 1778-1782 ◽

Cited By ~ 7

Author(s):

D. Tremouilles ◽

M. Bafleur ◽

G. Bertrand ◽

N. Nolhier ◽

N. Mauran ◽

...

Keyword(s):

Electrostatic Discharge ◽

Design Guidelines ◽

Protection Scheme ◽

Esd Protection ◽

Latch Up

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Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

Nanoscale Research Letters ◽

10.1186/s11671-020-03437-3 ◽

2020 ◽

Vol 15 (1) ◽

Author(s):

Ruibo Chen ◽

Hongxia Liu ◽

Wenqiang Song ◽

Feibo Du ◽

Hao Zhang ◽

...

Keyword(s):

Integrated Circuit ◽

Low Voltage ◽

Cmos Technology ◽

Cmos Process ◽

Triggering Mechanism ◽

Esd Protection ◽

Tcad Simulation ◽

P Type ◽

28 Nm ◽

Latch Up

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

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A latch-up free LVTSCR with improved overshoot characteristic for ESD protection in 40-nm CMOS process

Semiconductor Science and Technology ◽

10.1088/1361-6641/abf3a9 ◽

2021 ◽

Author(s):

Rui-Bo Chen ◽

Hong-Xia Liu ◽

Dan Guo ◽

Wei Huang ◽

Xiao-Zong Huang ◽

...

Keyword(s):

Cmos Process ◽

Esd Protection ◽

Latch Up

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