Mixture of negative bias temperature instability and hot-carrier driven threshold voltage degradation of 130nm technology p-channel transistors

2014 ◽  
Vol 54 (9-10) ◽  
pp. 2310-2314 ◽  
Author(s):  
Gunnar Andreas Rott ◽  
Karina Rott ◽  
Hans Reisinger ◽  
Wolfgang Gustin ◽  
Tibor Grasser
Keyword(s):  
Threshold Voltage ◽  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Temperature Instability ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Voltage Degradation ◽  
Threshold Voltage Degradation

scholarly journals Impact of Mixed Negative Bias Temperature Instability and Hot Carrier Stress on MOSFET Characteristics—Part I: Experimental

2019 ◽  
Vol 66 (1) ◽  
pp. 232-240 ◽  
Author(s):  
Bianka Ullmann ◽  
Markus Jech ◽  
Katja Puschkarsky ◽  
Gunnar Andreas Rott ◽  
Michael Waltl ◽  
...  
Keyword(s):  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Temperature Instability ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Hot Carrier Stress

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

2016 ◽  
Vol 4 (1) ◽  
pp. 01-05
Author(s):  
S Suvarna ◽  
K Rajesh ◽  
T Radhu
Keyword(s):  
Threshold Voltage ◽  
High Speed ◽  
Negative Bias ◽  
Positive Bias ◽  
Negative Bias Temperature Instability ◽  
Discrete Cosine Transforms ◽  
Temperature Instability ◽  
Booth Multiplier ◽  
Bias Temperature Instability ◽  
Digital Multipliers

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

scholarly journals On the Prediction of the Threshold Voltage Degradation in CMOS Technology Due to Bias-Temperature Instability

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 427 ◽  
Author(s):  
Alejandro Campos-Cruz ◽  
Guillermo Espinosa-Flores-Verdad ◽  
Alfonso Torres-Jacome ◽  
Esteban Tlelo-Cuautle
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Lookup Table ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Mos Devices ◽  
Voltage Degradation ◽  
Threshold Voltage Degradation

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.

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