Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

2017 ◽  
Vol 104 ◽  
pp. 470-476 ◽  
Author(s):  
J. Charles Pravin ◽  
D. Nirmal ◽  
P. Prajoon ◽  
N. Mohan Kumar ◽  
J. Ajayan
Keyword(s):  
Memory Circuit ◽  
Nano Scale ◽  
High K ◽  
Junctionless Transistor ◽  
Sram Memory

Breakdowns in high-k gate stacks of nano-scale CMOS devices

2005 ◽  
Vol 80 ◽  
pp. 353-361 ◽  
Author(s):  
K.L. Pey ◽  
R. Ranjan ◽  
C.H. Tung ◽  
L.J. Tang ◽  
V.L. Lo ◽  
...  
Keyword(s):  
Gate Stacks ◽  
Nano Scale ◽  
High K

scholarly journals Nano-Scale Characterization of Poly-Si Gate on High-k Gate Stack Structures by Scanning Photoemission Microscopy

2011 ◽  
Vol 9 ◽  
pp. 224-227 ◽  
Author(s):  
S. Toyoda ◽  
Y. Nakamura ◽  
K. Horiba ◽  
H. Kumigashira ◽  
M. Oshima ◽  
...  
Keyword(s):  
Gate Stack ◽  
Nano Scale ◽  
High K ◽  
Scale Characterization
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