Passivation of InP/GaAsSb/InP double heterostructure bipolar transistors with ultra thin base layer by low-temperature deposited SiNx

ABSTRACTA tri-level resist scheme using low temperature (<50°C) deposited SiNx ratfier than Ge for the transfer layer has been developed. This allows use of an optical stepper for lithographic patterning of the emitter-base junctions in GaAs/AlGaAs heterojunction bipolar transistors (HBTs) where a conventional lift-off process using a single level resist often leads to die presence of shorts between metallizations. The plasma-enhanced chemically vapor deposited (PECVD) SiNx shows a sligtly larger degree of Si-H bonding compared to nitride deposited at higher temperature (275°C), and is under compressive stress (-5 × 1010 dyne · cm−2) which is considerably relieved upor thermal cycling to 500°C (-1.5 × 1010 dyne · cm−2 after cool-down). This final stress is approximately a factor of two higher man conventional PECVD SiNx cycled in the same manner. The adhesion of the low temperature nitride to die underlying polydimediylglutarimide (PMGI) base layer in the tri-level resist is excellent, leading to high yields in the lift-off metallization process. These layers are etched in Electron Cyclotron Resonance (ECR) discharges of SF6 or O2, respectively, using low additional dc bias (≤-100V) on the sample. Subsequent deposition of the HBT base metallization (Ti/Ag/Au) and lift-off of the tri-level resist produces contacts with excellent edge definition and an absence of shorts between metallization.

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Comparison of the passivation effects on self- and non-self-aligned InP/InGaAs/InP double heterostructure bipolar transistors by low-temperature deposited SiNx

Journal of Applied Physics ◽

10.1063/1.1757656 ◽

2004 ◽

Vol 96 (1) ◽

pp. 777-783 ◽

Cited By ~ 9

Author(s):

Z. Jin ◽

W. Prost ◽

S. Neumann ◽

F.-J. Tegude

Keyword(s):

Low Temperature ◽

Bipolar Transistors ◽

Double Heterostructure

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20 Gbit/s regenerative receiver IC using InP/InGaAs double-heterostructure bipolar transistors

Electronics Letters ◽

10.1049/el:19970101 ◽

1997 ◽

Vol 33 (2) ◽

pp. 159 ◽

Cited By ~ 2

Author(s):

E. Sano ◽

K. Kurishima ◽

S. Yamahata

Keyword(s):

Bipolar Transistors ◽

Double Heterostructure

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Silicon Bipolar Transistors Fabricated using Ion Implantation and Laser Annealing

MRS Proceedings ◽

10.1557/proc-1-375 ◽

1980 ◽

Vol 1 ◽

Author(s):

Nobuyoshi Natsuaki ◽

Takao Miyazaki ◽

Makoto Ohkura ◽

Toru Nakamura ◽

Masao Tamura ◽

...

Keyword(s):

Low Temperature ◽

Laser Pulse ◽

Laser Irradiation ◽

Ruby Laser ◽

Laser Annealing ◽

Bipolar Transistors ◽

Pulse Irradiation ◽

Irradiation Effects ◽

Furnace Annealing ◽

Temperature Furnace

ABSTRACTBipolar transistors with laser annealed base and emitter, as well as those with furnace annealed base and laser annealed emitter, have been successfully fabricated using Q-switched ruby laser pulse irradiation. The performance of laser asannealed transistors is rather poor. However, it can be improved, to some extent, by relatively low temperature furnace annealing after laser irradiation. DC and RF characteristics of laser annealed transistors are presented in conjunction with laser irradiation effects on the characteristics of conventionally fabricated transistors.

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Prevention of InP/InGaAs/InP Double Heterojunction Bipolar Transistors from Current Gain Reduction during Passivation

MRS Proceedings ◽

10.1557/proc-833-g3.7 ◽

2004 ◽

Vol 833 ◽

Author(s):

Byoung-Gue Min ◽

Jong-Min Lee ◽

Seong-Il Kim ◽

Chul-Won Ju ◽

Kyung-Ho Lee

Keyword(s):

Heterojunction Bipolar Transistors ◽

Silicon Oxide ◽

Surface Recombination ◽

Surface States ◽

Bipolar Transistors ◽

Base Layer ◽

Current Gain ◽

Device Structure ◽

Double Heterojunction ◽

Gain Reduction

ABSTRACTA significant degradation of current gain of InP/InGaAs/InP double heterojunction bipolar transistors was observed after passivation. The amount of degradation depended on the degree of surface exposure of the p-type InGaAs base layer according to the epi-structure and device structure. The deposition conditions such as deposition temperature, kinds of materials (silicon oxide, silicon nitride and aluminum oxide) and film thickness were not major variables to affect the device performance. The gain reduction was prevented by the BOE treatment before the passivation. A possible explanation of this behavior is that unstable non-stoichiometric surface states produced by excess In, Ga, or As after mesa etching are eliminated by BOE treatment and reduce the surface recombination sites.

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