Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2 )

Integration ◽  
2013 ◽  
Vol 46 (2) ◽  
pp. 211-217 ◽  
Author(s):  
Ali Zakerolhosseini ◽  
Morteza Nikooghadam
Keyword(s):  
Low Power ◽  
Finite Fields ◽  
High Speed ◽  
High Speed Design ◽  
Bit Serial

scholarly journals Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing

2012 ◽  
Vol 2 (3) ◽  
pp. 96-101
Author(s):  
Shilpa Sathish ◽  
C. Lakshminarayana
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Percentage Reduction ◽  
High Speed Design

The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts

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