Low power and high speed design issues of CMOS  Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor

2018 ◽  
Author(s):  
Surajit Bari ◽  
Debashis De ◽  
Angsuman Sarkar
Keyword(s):  
Low Power ◽  
Error Detection ◽  
Code Generation ◽  
High Speed ◽  
Channel Length ◽  
Hamming Code ◽  
Design Issues ◽  
Mos Transistor ◽  
Detection Circuit ◽  
High Speed Design

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Wong How Hwan ◽  
Vinny Lam Siu Fan ◽  
Yusmeeraz Yusof
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dna Hybridization ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Electrical Signal ◽  
Oxide Semiconductor ◽  
Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool. 

A high speed GaAs error-detection circuit for fiber-optic transmission systems

1988 ◽  
Vol 35 (9) ◽  
pp. 1405-1411
Author(s):  
H.P. Singh ◽  
R.A. Sadler ◽  
J.F. Naber ◽  
B.O. Johannessen
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Fiber Optic ◽  
Transmission Systems ◽  
Detection Circuit

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

scholarly journals Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing

2012 ◽  
Vol 2 (3) ◽  
pp. 96-101
Author(s):  
Shilpa Sathish ◽  
C. Lakshminarayana
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Percentage Reduction ◽  
High Speed Design

The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts

A Low-Power Edge Detection Technique for Sensor Wake-Up Applications

2015 ◽  
Vol 24 (10) ◽  
pp. 1550157 ◽  
Author(s):  
Yao Wang ◽  
Haibo Wang ◽  
Guangjun Wen
Keyword(s):  
Edge Detection ◽  
Low Power ◽  
Process Variations ◽  
Design Guidelines ◽  
Detection Sensitivity ◽  
Ultra Low Power ◽  
Mos Transistor ◽  
Detection Circuit ◽  
Current Change ◽  
Small Voltage

A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuits for coping with process variations and mismatches are discussed in the paper. Simulation results are presented to demonstrate the performance of the proposed circuit.

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