Low-Power and High-Speed Design of FinFET-Based MCML Delay Element

2022 ◽  
pp. 185-194
Author(s):  
Pragya Srivastava ◽  
Richa Yadav ◽  
Richa Srivastava
Keyword(s):  
Low Power ◽  
High Speed ◽  
Delay Element ◽  
High Speed Design

scholarly journals Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing

2012 ◽  
Vol 2 (3) ◽  
pp. 96-101
Author(s):  
Shilpa Sathish ◽  
C. Lakshminarayana
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Percentage Reduction ◽  
High Speed Design

The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts

Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2 )

Integration ◽  
2013 ◽  
Vol 46 (2) ◽  
pp. 211-217 ◽  
Author(s):  
Ali Zakerolhosseini ◽  
Morteza Nikooghadam
Keyword(s):  
Low Power ◽  
Finite Fields ◽  
High Speed ◽  
High Speed Design ◽  
Bit Serial

Energy Efficient Error Resilient Multiplier Using Low-power Compressors

2022 ◽  
Vol 27 (3) ◽  
pp. 1-26
Author(s):  
Skandha Deepsita S ◽  
Dhayala Kumar M ◽  
Noor Mahammad SK
Keyword(s):  
Low Power ◽  
High Speed ◽  
Energy Savings ◽  
Approximate Algorithm ◽  
Image Processing Algorithm ◽  
Acceptable Error ◽  
High Speed Design ◽  
The Cost ◽  
Error Profiles ◽  
Error Distance

The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n . The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n -bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.

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