An ultra-low quiescent current output capacitor-less low-dropout regulator with a novel slew-rate-enhanced circuit

2014 ◽  
Author(s):  
Yang Chen ◽  
Yizhong Yang ◽  
Longjie Du ◽  
Guangjun Xie ◽  
Xin Cheng ◽  
...  
Keyword(s):  
Slew Rate ◽  
Current Output ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor

A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC

2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI
Keyword(s):  
High Power ◽  
Power Supply ◽  
Cmos Process ◽  
High Loop ◽  
Wide Range ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor ◽  
Large Output ◽  
Supply Rejection

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

A capacitorless low-dropout regulator with enhanced slew rate and 4.5- $$\upmu \hbox {A}$$ μ A quiescent current

2016 ◽  
Vol 90 (1) ◽  
pp. 227-235 ◽  
Author(s):  
Jaejin Yeo ◽  
Khurram Javed ◽  
Jaeseong Lee ◽  
Jeongjin Roh ◽  
Jae-Do Park
Keyword(s):  
Slew Rate ◽  
Quiescent Current ◽  
Low Dropout Regulator

An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique

2014 ◽  
Vol 45 (6) ◽  
pp. 708-718 ◽  
Author(s):  
Yanhan Zeng ◽  
Yuankun Xu ◽  
Miaowang Zeng ◽  
Hong-Zhou Tan
Keyword(s):  
Slew Rate ◽  
Rate Enhancement ◽  
Enhancement Technique ◽  
Low Dropout Regulator ◽  
Output Capacitor

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

Integration ◽  
2014 ◽  
Vol 47 (2) ◽  
pp. 204-212 ◽  
Author(s):  
Rasoul Fathipour ◽  
Alireza Saberkari ◽  
Herminio Martinez ◽  
Eduard Alarcón
Keyword(s):  
Current Mode ◽  
Slew Rate ◽  
Current Output ◽  
Error Amplifier ◽  
Quiescent Current ◽  
Ldo Regulator

A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO

2015 ◽  
Vol 764-765 ◽  
pp. 471-475 ◽  
Author(s):  
Wei Bin Yang ◽  
Shao Jyun Xie ◽  
Han Hsien Wang
Keyword(s):  
Current Efficiency ◽  
Operational Amplifier ◽  
Output Voltage ◽  
Input Voltage ◽  
Control Loop ◽  
Load Current ◽  
Digitally Controlled ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor

The new digital control loop of the low-dropout regulator (LDO) is presented. It is composed of coarse tracking circuit and fine tracking circuit, and no external output capacitor is required to stabilize the control loop. The proposed method makes the quiescent current lower than conventional analog LDOs. The operational amplifier of the conventional LDO fails to operate at 0.7V, and the developed digital LDO in 0.18um CMOS achieved the 0.7V input voltage and 0.5V output voltage with 99.99% current efficiency and 2.6-μA quiescent current at 20mA load current. Therefore, the proposed DLDO is suitable for low power applications.

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