Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme

Integration ◽  
2018 ◽  
Vol 63 ◽  
pp. 148-159
Author(s):  
Yongsuk Choi ◽  
Gyunam Jeon ◽  
Yong-Bin Kim
Keyword(s):  
Low Power ◽  
Calibration Scheme ◽  
Transceiver Design ◽  
Self Calibration ◽  
On Chip ◽  
Signal Interface

A Low Power and Low Noise On-Chip Active RF Tracking Filter for Digital TV Tuner ICs

2011 ◽  
Vol E94-C (10) ◽  
pp. 1698-1701
Author(s):  
Yang SUN ◽  
Chang-Jin JEONG ◽  
In-Young LEE ◽  
Sang-Gug LEE
Keyword(s):  
Low Power ◽  
Digital Tv ◽  
Low Noise ◽  
On Chip ◽  
Tracking Filter

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals The case for low-power photonic networks on chip

2007 ◽  
Author(s):  
Assaf Shacham ◽  
Keren Bergman ◽  
Luca P. Carloni
Keyword(s):  
Low Power ◽  
Photonic Networks ◽  
Networks On Chip ◽  
On Chip

A new signaling technique for a low power on-chip SerDes transceivers

2010 ◽  
Author(s):  
Ezz El-Din Hussein ◽  
Sally Safwat ◽  
Maged Ghoneima ◽  
Yehea Ismail
Keyword(s):  
Low Power ◽  
On Chip

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses

2008 ◽  
Vol 55 (7) ◽  
pp. 1904-1910 ◽  
Author(s):  
Maged M. Ghoneima ◽  
Muhammad M. Khellah ◽  
James Tschanz ◽  
Yibin Ye ◽  
Nasser Kurd ◽  
...  
Keyword(s):  
Low Power ◽  
On Chip

Design of R3TOS based reliable low power network on chip

2017 ◽  
Author(s):  
N Poornima ◽  
Seetharaman Gopalakrishnan ◽  
Tughrul Arsalan ◽  
T. N. Prabakar ◽  
M. Santhi
Keyword(s):  
Low Power ◽  
Network On Chip ◽  
Power Network ◽  
On Chip

Serial-Link Bus: A Low-Power On-Chip Bus Architecture

2009 ◽  
Vol 56 (9) ◽  
pp. 2020-2032 ◽  
Author(s):  
M. Ghoneima ◽  
Y. Ismail ◽  
M.M. Khellah ◽  
J. Tschanz ◽  
V. De
Keyword(s):  
Low Power ◽  
Serial Link ◽  
On Chip ◽  
Bus Architecture
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