A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation

Integration ◽  
2019 ◽  
Vol 65 ◽  
pp. 175-188
Author(s):  
Manas Kumar Hati ◽  
Tarun Kanti Bhattacharyya
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Noise Cancellation ◽  
Delta Sigma ◽  
Loop Bandwidth ◽  
Pll Frequency Synthesizer

scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

scholarly journals Reducing the Phase-Noise In ΔΣ Fractional-N Synthezis – A Simulink Model

2017 ◽  
Vol 23 (3) ◽  
pp. 131-134
Author(s):  
Emil Teodoru
Keyword(s):  
Phase Noise ◽  
Fractional Part ◽  
Noise Cancellation ◽  
Quantization Noise ◽  
Reference Frequency ◽  
Simulink Model ◽  
Loop Bandwidth

AbstractThe resolution in fractional-N synthesis results as a fractional part of the reference frequency. This category of synthesizers permits a greater frefand a smaller N, a larger loop bandwidth, faster lock times and reduced output phase-noise. In ΔΣ fractional-N PLL’s the main problem is the specific quantization noise. To reduce them many techniques are used. The paper presents a Simulink model of the influence of the requantisation in the phase-noise cancellation process.

Design and development of Ka-band carrier generator for IRS applications

2014 ◽  
Vol 7 (6) ◽  
pp. 637-644
Author(s):  
Vabya Kumar Pandit ◽  
Chitra Ramamurthy ◽  
Sourabh Basu ◽  
Deepak V. Ingale
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Multiplier ◽  
Frequency Resolution ◽  
Frequency Signal ◽  
Band Frequency ◽  
Ka Band ◽  
X Band ◽  
Pll Frequency Synthesizer ◽  
Low Phase Noise

A Ka-band carrier generator using phase-locked loop (PLL) frequency synthesizer is presented in this paper. The design uses integer-N PLL chip PE83336 as the important hardware support. The key idea of generating Ka-band frequency signal with low-phase noise is to generate a high-quality X-band frequency signal using PLL frequency synthesizer and employ a frequency multiplier to deliver the high-frequency output at the desired frequency band. Experimental measurements of the frequency synthesizer demonstrate the excellent performance, which is achieved with the Ka-band output with a frequency resolution of 5.7 MHz and phase noise better than −70 dBc/Hz at 1 kHz.

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