scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

A 52-to-67 GHz dual-core push–push VCO in 40-nm CMOS

2018 ◽  
Vol 10 (7) ◽  
pp. 783-793 ◽  
Author(s):  
Vadim Issakov ◽  
Johannes Rimmelspacher ◽  
Saverio Trotta ◽  
Marc Tiebout ◽  
Amelie Hagelauer ◽  
...  
Keyword(s):  
Continuous Wave ◽  
Frequency Tuning ◽  
Second Harmonic ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Chip Area ◽  
Wave Radar ◽  
Dual Core

AbstractWe present a continuously tunable 52-to-67 GHz push–push dual-core voltage-controlled oscillator (VCO) in a 40 nm bulk complementary metal–oxide–semiconductor (CMOS) technology. The circuit is suitable for 60 GHz frequency-modulated-continuous-wave radar applications requiring a continuously tunable ultra-wide modulation bandwidth. The LC-tank inductor is used to couple the two VCO cores. The fundamental frequency of the VCO can be tuned from 26 to 33.5 GHz, which corresponds to a frequency tuning range of 25%. The second harmonic is extracted in a non-invasive way using a transformer. The primary side acts simultaneously as a second harmonic filter. The VCO achieves in measurement a low phase noise of −91.8 dBc/Hz at 1 MHz offset at 62 GHz and an output power of −20 dBm. The VCO including buffers dissipates in the dual-core operation mode 60 mA from a single 1.1 V supply and consumes a chip area of 0.58 mm2.

A Wideband Gain Linearized Microwave Voltage Controlled Oscillator with Low Phase Noise Variation in Nanometer CMOS Technology

2015 ◽  
Vol 24 (03) ◽  
pp. 1550024 ◽  
Author(s):  
Mohammed Aqeeli ◽  
Abdullah Alburaikan ◽  
Cahyo Muvianto ◽  
Xianjun Huang ◽  
Zhirun Hu
Keyword(s):  
Phase Noise ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Lower Phase ◽  
Nanometer Cmos ◽  
Digitally Controlled ◽  
Binary Weighted ◽  
Low Phase Noise

A wideband CMOS LC tank voltage-controlled oscillator (VCO) with low phase noise variations and a linearized gain has been designed using a new binary-weighted switched-capacitor and digitally-controlled varactor bank. The novel design has the advantages of more linear VCO frequency tuning, lower phase noise and reduced gain to variations in supply voltage. The proposed VCO has been designed using UMC 90-nm, 6-metal CMOS technology and features phase noise variation of less than 4.9 dBc/Hz. The VCO operates from 3.45 to 6.55 GHz, with phase noise of -133.4 dBc/Hz at a 1 MHz offset, a figure of merit (FoM) of -203.3 dBc/Hz, less than 41 dBm spurious harmonics, and a total VCO core current consumption of 1.18 mA from a 3.3 V voltage supply. To the authors' knowledge, this is the lowest phase noise variation ever reported.

scholarly journals A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1502
Author(s):  
Waseem Abbas ◽  
Zubair Mehmood ◽  
Munkyo Seo
Keyword(s):  
Frequency Synthesizer ◽  
Dead Zone ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Chip Area ◽  
V Band ◽  
Locking Range ◽  
Frequency Detector

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

scholarly journals A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers

2011 ◽  
Vol 2011 ◽  
pp. 1-7 ◽  
Author(s):  
Yusaku Ito ◽  
Kenichi Okada ◽  
Kazuya Masu
Keyword(s):  
Tuning Range ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Variable Gain ◽  
Continuous Frequency ◽  
Reconfigurable Radio ◽  
Lc Vco

This paper proposes a novel wideband LC-based voltage-controlled oscillator (VCO) for multistandard transceivers. The proposed VCO has a core LC-VCO and a tuning-range extension circuit, which consists of switches, a mixer, dividers, and variable gain combiners with a spurious rejection technique. The experimental results exhibit 0.98 to 6.6 GHz continuous frequency tuning with −206 dBc/Hz of FoMT, which is fabricated by using a 0.18 μm CMOS process. The frequency tuning range (FTR) is 149%, and the chip area is 800 μm × 540 μm.

scholarly journals Phase Noise Reduction Technique for ISM Band LC Oscillator Using Tail Current

2021 ◽  
Vol 12 ◽  
pp. 116-124
Author(s):  
Kruti Thakore ◽  
D. J. Shah ◽  
N. M. Devashrey
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Ieee 802.15.4 ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Total Power ◽  
Voltage Controlled Oscillator ◽  
Ism Band ◽  
Lc Oscillator ◽  
Total Power Consumption

This paper presents low phase noise, precise frequency tuning range LC Voltage controlled Oscillator (VCO) circuit of Phase lock loop, to support - IEEE 802.11a/b/g, Bluetooth, Zigbee and IEEE 802.15.4., operating on 2.4GHz ISM band (Industrial, Scientific, Medical). The presented circuit is implemented in Cadence virtuoso environment and using GPDK090 Library of 90nm CMOS Technology. The presented VCO is tuned at 2.4GHz frequency with tuning range of 80MHz. The measured Phase noise is -126.3dBc/Hz at 1MHz offset frequency. The total power consumption of the presented VCO is 4.7mw at 1V power supply.

scholarly journals ANALYSIS OF FREQUENCY SYNTHESISERS FOR MULTISTANDART WIRELESS TRANSCEIVER / DAŽNIO SINTEZATORIŲ DAUGIASTANDARČIAMS BEVIELIO RYŠIO SIŲSTUVAMS IR IMTUVAMS ANALIZĖ

2016 ◽  
Vol 8 (3) ◽  
pp. 302-307 ◽  
Author(s):  
Marijan Jurgo ◽  
Romualdas Navickas
Keyword(s):  
Figure Of Merit ◽  
Frequency Synthesizer ◽  
Cmos Technology ◽  
Wireless Transceivers ◽  
Frequency Locking ◽  
Wireless Transceiver ◽  
Loop Bandwidth ◽  
Charge Pump Pll ◽  
Chip Size ◽  
Better Than

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

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