COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing

2017 ◽

Cited By ~ 1

Author(s):

A Sasikumar ◽

R Muthaiah

Keyword(s):

Particle Swarm Optimization ◽

Operational Amplifier ◽

Particle Swarm ◽

Nsga Ii ◽

Swarm Optimization ◽

Amplifier Circuit ◽

Circuit Sizing

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Energy optimization of pipelined digital systems using circuit sizing and supply scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2005.863760 ◽

2006 ◽

Vol 14 (2) ◽

pp. 122-134 ◽

Cited By ~ 28

Author(s):

H.Q. Dao ◽

B.R. Zeydel ◽

V.G. Oklobdzija

Keyword(s):

Energy Optimization ◽

Digital Systems ◽

Circuit Sizing

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Adaptive response surface modeling-based method for analog circuit sizing

IEEE International SOC Conference, 2004. Proceedings. ◽

10.1109/socc.2004.1362368 ◽

2004 ◽

Author(s):

Donghoon Han ◽

A. Chattejee

Keyword(s):

Response Surface ◽

Adaptive Response ◽

Analog Circuit ◽

Surface Modeling ◽

Response Surface Modeling ◽

Circuit Sizing

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Process Variation-Aware Analog Circuit Sizing: Uncertain Optimization

Automated Design of Analog and High-frequency Circuits - Studies in Computational Intelligence ◽

10.1007/978-3-642-39162-0_5 ◽

2013 ◽

pp. 85-105

Author(s):

Bo Liu ◽

Georges Gielen ◽

Francisco V. Fernández

Keyword(s):

Analog Circuit ◽

Process Variation ◽

Circuit Sizing ◽

Uncertain Optimization

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AIDA-C Layout-Aware Circuit Sizing Results

Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects ◽

10.1007/978-3-319-42037-0_7 ◽

2016 ◽

pp. 147-175

Author(s):

Nuno Lourenço ◽

Ricardo Martins ◽

Nuno Horta

Keyword(s):

Circuit Sizing

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NEC ampacity tables, circuit sizing, and developing standardized tables

IEEE Transactions on Industry Applications ◽

10.1109/28.55976 ◽

1990 ◽

Vol 26 (3) ◽

pp. 450-462

Author(s):

R.A. Fuselier

Keyword(s):

Circuit Sizing

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DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing

Journal of Global Optimization ◽

10.1007/s10898-008-9307-9 ◽

2008 ◽

Vol 44 (1) ◽

pp. 53-77 ◽

Cited By ~ 13

Author(s):

Jernej Olenšek ◽

Árpád Bűrmen ◽

Janez Puhan ◽

Tadej Tuma

Keyword(s):

Global Optimization ◽

Integrated Circuit ◽

Optimization Method ◽

Global Optimization Method ◽

Analog Integrated Circuit ◽

Circuit Sizing

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AIDA-PEx: Accurate parasitic extraction for layout-aware analog integrated circuit sizing

2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) ◽

10.1109/prime.2015.7251351 ◽

2015 ◽

Cited By ~ 2

Author(s):

Bruno Cardoso ◽

Ricardo Martins ◽

Nuno Lourenco ◽

Nuno Horta

Keyword(s):

Integrated Circuit ◽

Analog Integrated Circuit ◽

Parasitic Extraction ◽

Circuit Sizing

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Parasitic-aware gm/ID-based many-objective analog/RF circuit sizing

2018 19th International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2018.8357272 ◽

2018 ◽

Author(s):

Tuotian Liao ◽

Lihong Zhang

Keyword(s):

Circuit Sizing ◽

Rf Circuit

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A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 ◽

10.23919/date.2017.7927115 ◽

2017 ◽

Cited By ~ 1

Author(s):

Andreas Gerlach ◽

Juergen Scheible ◽

Thoralf Rosahl ◽

Frank-Thomas Eitrich

Keyword(s):

Analog Circuits ◽

Selection Method ◽

Circuit Sizing ◽

Topology Selection

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COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing

Operational amplifier circuit sizing based on NSGA-II and particle swarm optimization

Energy optimization of pipelined digital systems using circuit sizing and supply scaling

Adaptive response surface modeling-based method for analog circuit sizing

Process Variation-Aware Analog Circuit Sizing: Uncertain Optimization

AIDA-C Layout-Aware Circuit Sizing Results

NEC ampacity tables, circuit sizing, and developing standardized tables

DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing

AIDA-PEx: Accurate parasitic extraction for layout-aware analog integrated circuit sizing

Parasitic-aware gm/ID-based many-objective analog/RF circuit sizing

A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example

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