scholarly journals Device quantization policy in variation-aware in-memory computing design

2022 ◽  
Vol 12 (1) ◽  
Author(s):  
Chih-Cheng Chang ◽  
Shao-Tzu Li ◽  
Tong-Lin Pan ◽  
Chia-Ming Tsai ◽  
I-Ting Wang ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
System Performance ◽  
Dynamic Range ◽  
Memory Window ◽  
Fine Tuning ◽  
Memory Devices ◽  
Area Efficiency ◽  
Multiple Cells ◽  
Algorithm Level

AbstractDevice quantization of in-memory computing (IMC) that considers the non-negligible variation and finite dynamic range of practical memory technology is investigated, aiming for quantitatively co-optimizing system performance on accuracy, power, and area. Architecture- and algorithm-level solutions are taken into consideration. Weight-separate mapping, VGG-like algorithm, multiple cells per weight, and fine-tuning of the classifier layer are effective for suppressing inference accuracy loss due to variation and allow for the lowest possible weight precision to improve area and energy efficiency. Higher priority should be given to developing low-conductance and low-variability memory devices that are essential for energy and area-efficiency IMC whereas low bit precision (< 3b) and memory window (< 10) are less concerned.

scholarly journals Device Quantization Policy and Power-Performance- Area Co-Optimization Strategy in Variation-Aware In-memory Computing Design

2021 ◽  
Author(s):  
Chih-Cheng Chang ◽  
Shao-Tzu Li ◽  
Tong-Lin Pan ◽  
Chia-Ming Tsai ◽  
I-Ting Wang ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
System Performance ◽  
Dynamic Range ◽  
Fine Tuning ◽  
Optimization Strategy ◽  
Power Performance ◽  
Area Efficiency ◽  
Performance Area ◽  
Multiple Cells ◽  
Algorithm Level

Abstract Device quantization of in-memory computing (IMC) that considers the non-negligible variation and finite dynamic range of practical memory technology is investigated, aiming for quantitatively co-optimizing system performance on accuracy, power, and area. Architecture- and algorithm-level solutions are taken into consideration. Weight-separate mapping, VGG-like algorithm, multiple cells per weight, and fine-tuning of the classifier layer are effective for suppressing inference accuracy loss due to variation and allow for the lowest possible weight precision to improve area and energy efficiency. Higher priority should be given to developing low-conductance and low-variability memory devices that are essential for energy and area-efficiency IMC whereas low bit precision (< 3b) and memory window (<10) are less concerned.

scholarly journals Solar Activity Observed with the New Nobeyama Radioheliograph

1993 ◽  
Vol 141 ◽  
pp. 310-320 ◽  
Author(s):  
Shinzo Enome ◽  
Hiroshi Nakajima ◽  
Kiyoto Shibasaki ◽  
Masanori Nishio ◽  
Toshiaki Takano ◽  
...  
Keyword(s):  
Solar Activity ◽  
Image Quality ◽  
System Integration ◽  
System Performance ◽  
Dynamic Range ◽  
Fine Tuning ◽  
Radio Interferometer ◽  
Solar Observations ◽  
Better Than ◽  
Full Disk

AbstractThe new Nobeyama Radioheliograph was completed in March 1992 after two years of construction. It is a T-shaped array operating as a multiple spacing grating-type radio interferometer at 17 GHz and is dedicated to full disk solar observations. Routine observations began in late June, 1992, after three months of system integration, fine tuning, and test observations. During the course of test observations it was shown that major items of the system performance exceeded the designed values, and that the image quality or the dynamic range of the images is better than the designed value. In the three months of routine observations two X-class flares, several M-class flares and a number of small flares were observed. In this report we present a summary of initial observational results and preliminary comparisons with YOHKOH HXT and SXT observations.

scholarly journals Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency

2018 ◽  
Vol 8 (4) ◽  
pp. 34 ◽  
Author(s):  
Vishal Saxena ◽  
Xinyu Wu ◽  
Ira Srivastava ◽  
Kehan Zhu
Keyword(s):  
Machine Learning ◽  
Energy Efficiency ◽  
Deep Learning ◽  
Large Scale ◽  
Learning Algorithms ◽  
Memory Devices ◽  
Cognitive Computing ◽  
Mixed Signal ◽  
Von Neumann ◽  
Emerging Memory

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.

Measured Performance of a Variable Transmission Glazing System

2019 ◽  
Author(s):  
Ali Al-Dossary ◽  
Heather Dillon ◽  
Jordan Farina
Keyword(s):  
Energy Efficiency ◽  
Cost Saving ◽  
System Performance ◽  
Temperature Gradients ◽  
Average Efficiency ◽  
Energy Efficiency Measures ◽  
Efficiency Measures ◽  
Variable Transmission ◽  
The University

Abstract Variable Transmission Glazing (VTG) windows are an energy efficiency measures that have relatively high first cost. This paper describes the in-situ performance of VTG installed in an atrium space at the University of Portland. An experiment was conducted using thermocouples and photosensors to examine temperature gradients and solar gains across electrochromic glazing windows to quantify the performance of the installed system in terms of energy and cost saving. The system performance was measured with an average efficiency of 98.73% when the VTG was operating. The annual savings of the glazing system installed was estimated to be $7,683.

scholarly journals Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

Small ◽  
2020 ◽  
Vol 16 (47) ◽  
pp. 2004907
Author(s):  
Taro Sasaki ◽  
Keiji Ueno ◽  
Takashi Taniguchi ◽  
Kenji Watanabe ◽  
Tomonori Nishimura ◽  
...  
Keyword(s):  
Gate Voltage ◽  
2D Materials ◽  
Memory Window ◽  
Floating Gate ◽  
Memory Devices

A correction code for multiple cells upsets in memory devices for space applications

2016 ◽  
Author(s):  
Helano de S. Castro ◽  
Jarbas A. N. da Silveira ◽  
Alexandre A. P. Coelho ◽  
Felipe G. A. e Silva ◽  
Philippe de S. Magalhaes ◽  
...  
Keyword(s):  
Memory Devices ◽  
Space Applications ◽  
Multiple Cells

Silicon Nanocrystalline Nonvolatile Memory - Characterization and Analysis

2016 ◽  
Vol 39 ◽  
pp. 134-150
Author(s):  
Valerii Ievtukh ◽  
A. Nazarov
Keyword(s):  
Nonvolatile Memory ◽  
Silicon Nanocrystals ◽  
Memory Window ◽  
Experimental Results ◽  
Memory Devices ◽  
Mos Capacitor ◽  
Mos Structure ◽  
Capacitance Voltage ◽  
Nonvolatile Memory Devices ◽  
Bipolar Memory

In this work, nanocrystal nonvolatile memory devices comprising of silicon nanocrystals located in gate oxide of MOS structure, were comprehensively studied on specialized modular data acquisition setup developed for capacitance-voltage measurements. The memory window formation, memory window retention and charge relaxation experimental methods were used to study the trapping/emission processes inside the dielectric layer of MOS capacitor memory. The trapping/emission processes were studied in standard bipolar memory mode and in new unipolar memory mode, which is specific for nanocrystalline nonvolatile memory. The analysis of experimental results shown that unipolar programming mode is more favourable for nanocrystalline memory operation due to lower wearing out and higher breakdown immunity of the MOS device’s oxide. The study was performed for two types of nanocrystalline memory devices: with one and two silicon nanocrystalline 2D layers in oxide of MOS structure correspondingly. The electrostatic modelling was presented to explain the experimental results.

The Experiment on System Performance Comparing Analysis and Displacement between R1270 and R22

2015 ◽  
Vol 799-800 ◽  
pp. 770-773
Author(s):  
Zhi Jiang Wu
Keyword(s):  
Energy Efficiency ◽  
Heat Exchanger ◽  
Performance Optimization ◽  
System Performance ◽  
Air Conditioning ◽  
Tube Diameter ◽  
Experimental Results ◽  
Efficiency Ratio

The refrigeration circle performance of air conditioning comparing analysis and displacement between R1270 and R22 is studied in this paper. In addition, the system performance optimization of R1270 refrigeration circle is discussed.The experimental results show that the smaller tube diameter of heat exchanger for R1270 system is easy to improve the energy efficiency ratio in the unimproved system.These results are important for theory and reality to research this type of air conditioning.

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