Ultrafast clock recovery technique for high-speed optical packet networks

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.

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Ultra-fast Clock Recovery Based on Pre-embedded Sub-harmonic Clock in Optical Burst/Packet Networks

OFC/NFOEC 2007 - 2007 Conference on Optical Fiber Communication and the National Fiber Optic Engineers Conference ◽

10.1109/ofc.2007.4348349 ◽

2007 ◽

Cited By ~ 1

Author(s):

S. B. Jun ◽

Paul K. J. Park ◽

Hoon Kim ◽

Y. C. Chung

Keyword(s):

Clock Recovery ◽

Packet Networks ◽

Optical Burst

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Clock recovery for high-speed optical communication

10.1117/12.229266 ◽

1996 ◽

Author(s):

Ken Pedrotti

Keyword(s):

Optical Communication ◽

High Speed ◽

Clock Recovery

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Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i3.12.16553 ◽

2018 ◽

Vol 7 (3.12) ◽

pp. 871

Author(s):

Thejusraj. H ◽

Prithivi Raj ◽

J Selvakumar ◽

S Praveen Kumar

Keyword(s):

Power Consumption ◽

High Frequency ◽

High Speed ◽

Phase Locked Loop ◽

Clock Recovery ◽

Ring Oscillator ◽

Voltage Controlled Oscillator ◽

Voltage Controlled Oscillators ◽

Clock Generation ◽

Consumption Values

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

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