Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach

Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.

Design of New Au–NiCo MEMS Vertical Probe for Fine-Pitch Wafer-Level Probing

As fine-pitch 3D wafer-level packaging becomes more popular in semiconductor industries, wafer-level prebond testing of various interconnect structures has become increasingly challenging. Additionally, improving the current-carrying capacity (CCC) and minimizing damage to the probe and micro-interconnect structures are very important issues in wafer-level testing. In this study, we propose an Au–NiCo MEMS vertical probe with an enhanced CCC to efficiently reduce the damage to the probe and various interconnect structures, including a solder ball, Cu pillar microbump, and TSV. The Au–NiCo probe has an Au layer inside the NiCo and an Au layer outside the surface of the NiCo probe to reduce resistivity and contact stress. The current-carrying capacity, contact stress, and deformation behavior of the probe and various interconnect structures were evaluated using numerical analyses. The Au–NiCo probe had a 150% higher CCC than the conventional NiCo probe. The maximum allowable current capacity of the 5000 µm-long Au–NiCo probe was 750 mA. The Au–NiCo probe exhibited less contact force and stress than the NiCo probe. The Au–NiCo probe also produced less deformation of various interconnect structures. These results indicate that the proposed Au–NiCo probe will be a prospective candidate for advanced wafer-level testing, with better probing efficiency and higher test yield and reliability than the conventional vertical probe.

Inhibiting Effects of the Ni Barrier Layer on the Growth of Porous Cu3sn in 10 μm Microbumps

With the shrinkage of size, porous Cu3Sn have become a new potential threat of the reliability in micron Cu pillar bump. The formation of porous Cu3Sn is contributed the decomposition of Cu6Sn5, which is caused by the overgrowth of intermetallic compounds (IMC) and the stress introduced by the phase transition of Cu6Sn5. In this paper, uniform Ф10 µm Cu/Sn and Cu/Ni (~0.6 μm)/Sn microbumps have been fabricated by multilayer electrodeposition and the effect of the Ni layer on the growth behavior of porous Cu3Sn was investigated by comparing the evolution of IMC in Cu/Sn and Cu/Ni/Sn bumps aged at 170 ℃ and 200 ℃. The ~0.6 μm Ni layer can effectively retard the Cu atoms diffusion, which can hinder IMC from overgrowth. Moreover, with the help of X-ray diffraction (XRD), the ability of the Ni layer in stabilizing Cu6Sn5 phase is strengthened, which weakens the tendency of the porous Cu3Sn formation. Under the conjoint action of retarding the growth of IMC and stabilizing Cu6Sn5 phase, the Ni layer can inhibit the formation of porous Cu3Sn efficaciously.

Optimization of High-Speed Electrolytic Plating of Copper Pillar to Achieve a Flat Top Morphology and Height Uniformity

Cu plating bath for high-speed electrodeposition of Cu pillar was designed in consideration of a flat top morphology of pillar and a pillar height uniformity. An ideal polarization curve was assumed for the flat top morphology. To obtain the ideal polarization curve, an effect of organic additive concentration and solution agitation on the polarization curve were investigated. The basic bath components were optimized considering a Wagner number to improve the pillar height uniformity. To confirm the pillar top morphology and the pillar height uniformity, a 300-mm diameter wafer was plated with Cu at 20 A/dm2. As a result, improved pillar top morphology and pillar height uniformity were obtained. The optimized plating bath was applied to the plating of a large-size panel of 415 × 510 mm.