Si Photonics Deployment Using Cu Pillar Interconnect and Chip On Wafer Platform

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.

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Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2014dpc-wp24 ◽

2014 ◽

Vol 2014 (DPC) ◽

pp. 001643-001669

Author(s):

Koji Tatsumi ◽

Kyouhei Mineo ◽

Takeshi Hatta ◽

Takuma Katase ◽

Masayuki Ishikawa ◽

...

Keyword(s):

High Speed ◽

Flip Chip ◽

New Technologies ◽

Short Circuit ◽

Lead Free Solder ◽

Cu Pillar ◽

Fine Pitch ◽

Different Shapes ◽

Free Solder ◽

High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

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High-speed and high-sensitivity parallel spectral-domain optical coherence tomography using a supercontinuum light source

Optics Letters ◽

10.1364/ol.41.005620 ◽

2016 ◽

Vol 41 (24) ◽

pp. 5620 ◽

Cited By ~ 18

Author(s):

Jessica Barrick ◽

Ana Doblas ◽

Michael R. Gardner ◽

Patrick R. Sears ◽

Lawrence E. Ostrowski ◽

...

Keyword(s):

Optical Coherence Tomography ◽

Light Source ◽

High Speed ◽

High Sensitivity ◽

Spectral Domain ◽

Optical Coherence ◽

Supercontinuum Light Source

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Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

International Symposium on Microelectronics ◽

10.4071/isom-2013-tp21 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000235-000235

Author(s):

Zhe Li ◽

Siow Chek Tan ◽

Yee Huan Yew ◽

Pheak Ti Teh ◽

MJ Lee ◽

...

Keyword(s):

High Speed ◽

High Performance ◽

Flip Chip ◽

Low Cost ◽

Electrical Performance ◽

Package Design ◽

Cu Pillar ◽

Fine Pitch ◽

Field Programmable ◽

Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

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Rapid Online Buffer Exchange: A Method for Screening of Proteins, Protein Complexes, and Cell Lysates by Native Mass Spectrometry

10.26434/chemrxiv.8792177 ◽

2019 ◽

Author(s):

Zachary VanAernum ◽

Florian Busch ◽

Benjamin J. Jones ◽

Mengxuan Jia ◽

Zibo Chen ◽

...

Keyword(s):

Mass Spectrometry ◽

High Speed ◽

Structural Information ◽

Protein Complexes ◽

High Sensitivity ◽

Native Mass Spectrometry ◽

Structural Features ◽

Consumer Products ◽

Cell Lysates ◽

Protein Expression And Purification

It is important to assess the identity and purity of proteins and protein complexes during and after protein purification to ensure that samples are of sufficient quality for further biochemical and structural characterization, as well as for use in consumer products, chemical processes, and therapeutics. Native mass spectrometry (nMS) has become an important tool in protein analysis due to its ability to retain non-covalent interactions during measurements, making it possible to obtain protein structural information with high sensitivity and at high speed. Interferences from the presence of non-volatiles are typically alleviated by offline buffer exchange, which is timeconsuming and difficult to automate. We provide a protocol for rapid online buffer exchange (OBE) nMS to directly screen structural features of pre-purified proteins, protein complexes, or clarified cell lysates. Information obtained by OBE nMS can be used for fast (<5 min) quality control and can further guide protein expression and purification optimization.

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Wafer-Scale Flexible Plasmonic Metasurface with Passivated Aluminum Nanopillars for High-Sensitivity Immunosensors

Sensors and Actuators B Chemical ◽

10.1016/j.snb.2021.130170 ◽

2021 ◽

pp. 130170

Author(s):

Fangfei Jiao ◽

Fajun Li ◽

Jiaqing Shen ◽

Chaoheng Guan ◽

Sayed Ali Khan ◽

...

Keyword(s):

High Sensitivity ◽

Wafer Scale

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Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽

10.3390/mi12030295 ◽

2021 ◽

Vol 12 (3) ◽

pp. 295

Author(s):

Pao-Hsiung Wang ◽

Yu-Wei Huang ◽

Kuo-Ning Chiang

Keyword(s):

Finite Element ◽

Thermal Cycling ◽

Glass Substrate ◽

High Speed ◽

Coefficient Of Thermal Expansion ◽

Three Dimensional ◽

Design Parameters ◽

Time To Failure ◽

Wafer Level ◽

Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

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