Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array

2018 ◽  
pp. 151-161 ◽  
Author(s):  
Inderpreet Kaur ◽  
Lakshay Rohilla ◽  
Alisha Nagpal ◽  
Bishwajeet Pandey ◽  
Sanchit Sharma
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Memory Design ◽  
Field Programmable ◽  
Gate Array ◽  
Capacitance Scaling ◽  
28 Nm

Nonvolatile Configuration Memory Cell for Low Power Field Programmable Gate Array

2011 ◽  
Author(s):  
Shinichi Yasuda ◽  
Kazutaka Ikegami ◽  
Tetsufumi Tanamoto ◽  
Atsuhiro Kinoshita ◽  
Keiko Abe ◽  
...  
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Memory Cell ◽  
Field Programmable ◽  
Gate Array

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

2016 ◽  
Vol 10 (3) ◽  
pp. 163-172 ◽  
Author(s):  
Zarrin Tasnim Sworna ◽  
Mubin UlHaque ◽  
Nazma Tara ◽  
Hafiz Md. Hasan Babu ◽  
Ashis Kumar Biswas
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Look Up Table ◽  
Field Programmable ◽  
Decimal Adder ◽  
Gate Array ◽  
Area Efficient

scholarly journals A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array

2020 ◽  
Vol 91 (2) ◽  
pp. 024708 ◽  
Author(s):  
Xi Qin ◽  
Ming-Dong Zhu ◽  
Wen-Zhe Zhang ◽  
Yi-Heng Lin ◽  
Ying Rui ◽  
...  
Keyword(s):  
High Resolution ◽  
Field Programmable Gate Array ◽  
Resolution Time ◽  
Field Programmable ◽  
Gate Array ◽  
28 Nm
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