Physics‐based simulation study of high‐performance gallium arsenide phosphide–indium gallium arsenide tunnel field‐effect transistor

2016 ◽  
Vol 11 (7) ◽  
pp. 366-368 ◽  
Author(s):  
Bhagwan Ram Raad ◽  
Dheeraj Sharma ◽  
Kaushal Nigam ◽  
Pravin Kondekar
Keyword(s):  
Gallium Arsenide ◽  
Indium Gallium Arsenide ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Gallium Arsenide Phosphide ◽  
Effect Transistor ◽  
Indium Gallium ◽  
Tunnel Field Effect Transistor ◽  
Physics Based Simulation

Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

RSC Advances ◽  
2014 ◽  
Vol 4 (43) ◽  
pp. 22803-22807 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Bahniman Ghosh ◽  
Shiromani Bal Mukund Rahi ◽  
Yogesh Goswami
Keyword(s):  
Optimal Design ◽  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor using HfO2 as a gate dielectric.

scholarly journals High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 75 ◽  
Author(s):  
Xiaoling Duan ◽  
Jincheng Zhang ◽  
Jiabo Chen ◽  
Tao Zhang ◽  
Jiaduo Zhu ◽  
...  
Keyword(s):  
Energy Band ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Energy Band Structure ◽  
Drain Region ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Silvaco Atlas ◽  
Channel Region

A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET.

A high performance gate engineered charge plasma based tunnel field effect transistor

2015 ◽  
Vol 14 (2) ◽  
pp. 477-485 ◽  
Author(s):  
Faisal Bashir ◽  
Sajad A. Loan ◽  
M. Rafat ◽  
Abdul Rehman M. Alamoud ◽  
Shuja A. Abbasi
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Charge Plasma ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor
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