Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

RSC Advances ◽  
2014 ◽  
Vol 4 (43) ◽  
pp. 22803-22807 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Bahniman Ghosh ◽  
Shiromani Bal Mukund Rahi ◽  
Yogesh Goswami
Keyword(s):  
Optimal Design ◽  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor using HfO2 as a gate dielectric.

Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications

RSC Advances ◽  
2015 ◽  
Vol 5 (60) ◽  
pp. 48779-48785 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Yogesh Goswami ◽  
Shibir Basak ◽  
Shiromani Balmukund Rahi ◽  
Bahniman Ghosh
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Improved Performance

In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure.

Ge-Source Based L-Shaped Tunnel Field Effect Transistor for Low Power Switching Application

2021 ◽  
Author(s):  
Sweta Chander ◽  
Sanjeet Kumar Sinha ◽  
Rekha Chaudhary ◽  
Avtar Singh
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Bandgap Engineering ◽  
Power Switching ◽  
Current Threshold ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract In this work, the performance of the heterojunction L-Tunnel Field Effect Transistor (LTFET) has been analyzed with different engineering techniques such as bandgap engineering, pocket engineering, work-function engineering, and gate dielectric engineering, respectively. The electrical characteristics of the device has been investigated by using Synopsys Sentaurus TCAD tool and compared with some recent other TFETs. The proposed Ge-source L-TFET device with n-type pocket shows ON-state current of 2.12*10-5 Aµm-1, OFF-state current of 1.09*10-13 Aµm-1, current ratio of ~108 and sub-threshold slope (SS) of 21 mV/decade and the threshold voltage of 0.26 V and compared to the conventional Si/Ge source L-shaped TFETs without pocket simulation result. The pocket engineering techniques suppress the leakage without degrading the ON current, threshold voltage and SS of the proposed device. The simplified fabrication steps of the proposed device have also been discussed. The proposed L-TFET is free from ambipolarity issues and can be used to develop low-power switching devices.

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