A room temperature strategy towards enhanced performance and bias stability of oxide thin film transistor with a sandwich structure channel layer

2017 ◽  
Vol 110 (15) ◽  
pp. 153503 ◽  
Author(s):  
Yong Zeng ◽  
Honglong Ning ◽  
Zeke Zheng ◽  
Hongke Zhang ◽  
Zhiqiang Fang ◽  
...  
Keyword(s):  
Thin Film ◽  
Sandwich Structure ◽  
Room Temperature ◽  
Thin Film Transistor ◽  
Oxide Thin Film ◽  
Channel Layer ◽  
Bias Stability ◽  
Structure Channel

Influence of the channel layer thickness on electrical properties of indium zinc oxide thin-film transistor

2010 ◽  
Vol 87 (10) ◽  
pp. 2019-2023 ◽  
Author(s):  
Ai Hua Chen ◽  
Hong Tao Cao ◽  
Hai Zhong Zhang ◽  
Ling Yan Liang ◽  
Zhi Min Liu ◽  
...  
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Electrical Properties ◽  
Layer Thickness ◽  
Thin Film Transistor ◽  
Oxide Thin Film ◽  
Zinc Oxide Thin Film ◽  
Channel Layer ◽  
Indium Zinc Oxide

scholarly journals High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer

Nanomaterials ◽  
2020 ◽  
Vol 10 (11) ◽  
pp. 2145 ◽  
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Thin Film Transistor ◽  
Three Dimensional ◽  
Random Access ◽  
Oxide Thin Film ◽  
Amorphous Sio2 ◽  
Sio2 Substrate ◽  
Channel Layer

Metal-oxide thin-film transistors (TFTs) have been implanted for a display panel, but further mobility improvement is required for future applications. In this study, excellent performance was observed for top-gate coplanar binary SnO2 TFTs, with a high field-effect mobility (μFE) of 136 cm2/Vs, a large on-current/off-current (ION/IOFF) of 1.5 × 108, and steep subthreshold slopes of 108 mV/dec. Here, μFE represents the maximum among the top-gate TFTs made on an amorphous SiO2 substrate, with a maximum process temperature of ≤ 400 °C. In contrast to a bottom-gate device, a top-gate device is the standard structure for monolithic integrated circuits (ICs). Such a superb device integrity was achieved by using an ultra-thin SnO2 channel layer of 4.5 nm and an HfO2 gate dielectric with a 3 nm SiO2 interfacial layer between the SnO2 and HfO2. The inserted SiO2 layer is crucial for decreasing the charged defect scattering in the HfO2 and HfO2/SnO2 interfaces to increase the mobility. Such high μFE, large ION, and low IOFF top-gate SnO2 devices with a coplanar structure are important for display, dynamic random-access memory, and monolithic three-dimensional ICs.

The Influence of the Hafnium Doping on Negative Bias Stability in Zinc Oxide Thin Film Transistor

2010 ◽  
Vol 13 (9) ◽  
pp. H295 ◽  
Author(s):  
Woong-Sun Kim ◽  
Yeon-Keon Moon ◽  
Kyung-Taek Kim ◽  
Sae-Young Shin ◽  
Byung Du Ahn ◽  
...  
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistor ◽  
Oxide Thin Film ◽  
Negative Bias ◽  
Zinc Oxide Thin Film ◽  
Bias Stability

Effects of channel thickness on oxide thin film transistor with double-stacked channel layer

2017 ◽  
Vol 71 (9) ◽  
pp. 561-564 ◽  
Author(s):  
Kimoon Lee ◽  
Yong-Hoon Kim ◽  
Sung-Min Yoon ◽  
Jiwan Kim ◽  
Min Suk Oh
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Oxide Thin Film ◽  
Channel Layer ◽  
Channel Thickness
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