Design and simulation of low power flip flop in nanometer regime

2020 ◽  
Author(s):  
Vrinda Vijayakumar ◽  
K. R. Ajayan
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Nanometer Regime

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

2021 ◽  
Author(s):  
Yugal Maheshwari ◽  
Kleber Stangherlin ◽  
Derek Wright ◽  
Manoj Sachdev
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Low Energy ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

2019 ◽  
Vol 54 (2) ◽  
pp. 550-559 ◽  
Author(s):  
Yunpeng Cai ◽  
Anand Savanth ◽  
Pranay Prabhat ◽  
James Myers ◽  
Alex S. Weddell ◽  
...  
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
Ultra Low Power
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