A CMOS phase/frequency detector with a high-speed low-power D-type master-slave flip-flop

2004 ◽  
Author(s):  
Yubtzuan Chen ◽  
Chih Ho Tu ◽  
Jein Wu
Keyword(s):  
Low Power ◽  
High Speed ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Frequency Detector

PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

2020 ◽  
Vol 13 (4) ◽  
pp. 516-530
Author(s):  
Suraj K. Saw ◽  
Madhusudan Maiti ◽  
Preetisudha Meher ◽  
Alak Majumder
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Dead Zone ◽  
Cmos Technology ◽  
Switching Noise ◽  
Phase Frequency Detector ◽  
Layout Area ◽  
Frequency Detector ◽  
Lock In

Background & Introduction: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors. Methods: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node. This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology. Results: The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V. Conclusion: Process Variation analysis performed proves the robustness of the proposed circuit at all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.

scholarly journals Implementation of Phase Frequency Detector in Phase locked loop using Preset able modified TSPC D flip-flop

2019 ◽  
Vol 8 (12) ◽  
pp. 977-980
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Single Phase ◽  
Phase Locked Loop ◽  
Frequency Multiplier ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
Technology Applications ◽  
Phase Clock ◽  
Frequency Detector

Phase locked loop (PLL) forms an important part in many applications. Here design of PLL for frequency multiplier operation is considered. Frequency multiplier operation is implemented by using Preset able Modified Single Phase Clock (MTSPC) D flipflop logic circuits in Phase Frequency Detector (PFD). Preset able Modified Single Phase Clock (MTSPC) D flipflops functions at high speed with less power consumption. Noises in the form of glitches are introduced when a preset-able true single phase clocked D flipflop (TSPC) used in Phase Locked Loop. Preset-able modified TSPC (MTSPC) D flipflop used to overcome these glitches caused due to toggling at the output by use of PMOS. Technology applied is 90nm technology. Applications where better speed and reduced power consumption are required, this type of Phase locked loop (PLL) can be utilized.

scholarly journals High‐speed, low power, and dead zone improved phase frequency detector

2019 ◽  
Vol 13 (7) ◽  
pp. 1056-1062 ◽  
Author(s):  
Amir Fathi ◽  
Morteza Mousazadeh ◽  
Abdollah Khoei
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dead Zone ◽  
Phase Frequency Detector ◽  
Frequency Detector
Sign in / Sign up

Export Citation Format

Share Document