Die-level, post-CMOS processes for fabricating open-gate, field-effect biosensor arrays with on-chip circuitry

2008 ◽  
Vol 18 (11) ◽  
pp. 115032 ◽  
Author(s):  
S R Chang ◽  
C H Chang ◽  
J S Lin ◽  
S C Lu ◽  
Y T Lee ◽  
...  
2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Monica Bollani ◽  
Marco Salvalaglio ◽  
Abdennacer Benali ◽  
Mohammed Bouabdellaoui ◽  
Meher Naffouti ◽  
...  

AbstractLarge-scale, defect-free, micro- and nano-circuits with controlled inter-connections represent the nexus between electronic and photonic components. However, their fabrication over large scales often requires demanding procedures that are hardly scalable. Here we synthesize arrays of parallel ultra-long (up to 0.75 mm), monocrystalline, silicon-based nano-wires and complex, connected circuits exploiting low-resolution etching and annealing of thin silicon films on insulator. Phase field simulations reveal that crystal faceting and stabilization of the wires against breaking is due to surface energy anisotropy. Wires splitting, inter-connections and direction are independently managed by engineering the dewetting fronts and exploiting the spontaneous formation of kinks. Finally, we fabricate field-effect transistors with state-of-the-art trans-conductance and electron mobility. Beyond the first experimental evidence of controlled dewetting of patches featuring a record aspect ratio of $$\sim$$~1/60000 and self-assembled $$\sim$$~mm long nano-wires, our method constitutes a distinct and promising approach for the deterministic implementation of atomically-smooth, mono-crystalline electronic and photonic circuits.


2015 ◽  
Vol 212 (6) ◽  
pp. 1313-1319 ◽  
Author(s):  
Thanh Chien Nguyen ◽  
Miriam Schwartz ◽  
Xuan Thang Vu ◽  
Jörg Blinn ◽  
Sven Ingebrandt

2011 ◽  
Vol 6 (1) ◽  
Author(s):  
Stefan M Harazim ◽  
Ping Feng ◽  
Samuel Sanchez ◽  
Christoph Deneke ◽  
Yongfeng Mei ◽  
...  

NANO ◽  
2015 ◽  
Vol 10 (02) ◽  
pp. 1550027 ◽  
Author(s):  
Avik Chakraborty ◽  
Angsuman Sarkar

This paper presents the analog/RF performance for an III–V semiconductor-based staggered hetero-tunnel-junction n-type nanowire (NW) tunneling field effect transistor (n-TFET), for the first time. The device parameters for analog/mixed-signaling applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/I DS ), output resistance (R out ), intrinsic gain and unity-gain cutoff frequency (fT) are studied for III–V based NW n-TFET, with the help of device simulator and compared with those for a similarly sized homojunction (HJ) NW n-TFET. The result reveals that the hetero-tunnel-junction n-TFETs outperform their HJ counterparts for analog/mixed-signal system-on-chip (SoC) applications.


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