Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.

Impact of Gate Offset in Gate Recess on DC and RF Performance of InAlAs/InGaAs InP-based HEMTs

In this work, a set of 100-nm gate-length InP-based HEMTs were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (Ids,max) and transconductance (gm,max) increased. In the meantime, f T decreased while f max increased, and the highest f max of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usage.

Investigation of DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

In this paper, a C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effect of pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current (I on ), on/off current ratio (I on /I off ), subthreshold swing (SS), transconductance (g m ), cut-off frequency (f T ), and gain-bandwidth product (GBP) are investigated. The optimized CSP-TFET device exhibits excellent performance with high I on (9.98×10-4 A/μm), high I on /I off (~1011), as well as low SS (~12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.

CMOS voltage-controlled oscillator with high-performance MEMS tunable inductor

LC CMOS voltage-controlled oscillators (VCOs) with tunable inductors are essential for high-performance, multi-band communication systems, such as IoT applications and 5G communication. However, VCOs that use CMOS tunable inductors have difficulty in achieving high RF performance due to the low Q-factor of the inductor. In addition, previously reported CMOS VCOs integrated with MEMS inductors have used CMOS switches for tuning frequency bands, but they also had large signal losses on the switch. Herein, we propose a CMOS VCO that is integrated with a MEMS tunable inductor that tunes the frequency band with three MEMS switches. The proposed MEMS tunable inductor enables us to achieve high RF performance due to the suspended structure, and RF MEMS switches enable lower signal loss than CMOS switches. In this work, we successfully fabricated the proposed CMOS VCO integrated with a MEMS tunable inductor using the flip-chip bonding process, and we measured oscillation frequencies according to the actuation of the three switches. The oscillation powers were measured as − 3.03 dBm @ 1.39 GHz, − 5.80 @ 1.98 GHz, − 7.44 dBm @ 2.81 GHz, and − 8.77 dBm @ 3.68 GHz.

Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog applications

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.