A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

2011 ◽  
Vol 32 (1) ◽  
pp. 015006 ◽  
Author(s):  
Jinshan Yu ◽  
Ruitao Zhang ◽  
Zhengping Zhang ◽  
Yonglu Wang ◽  
Can Zhu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Digital Calibration ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Calibration Technique ◽  
Wide Bandwidth ◽  
Analog To Digital ◽  
Ultra High Speed

scholarly journals A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 165
Author(s):  
Shouping Li ◽  
Yang Guo ◽  
Jianjun Chen ◽  
Bin Liang
Keyword(s):  
Successive Approximation ◽  
High Speed ◽  
Low Noise ◽  
Digital Calibration ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Calibration Algorithm

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

scholarly journals DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH

2012 ◽  
pp. 51-56
Author(s):  
CHANNAKKA LAKKANNAVAR ◽  
SHRIKANTH K. SHIRAKOL ◽  
KALMESHWAR N. HOSUR
Keyword(s):  
Data Storage ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Input Voltage ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.

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