scholarly journals Improved Design of a 4-bit Absolute-Value Detector Using Simplified Chain Carry Adder

2021 ◽  
Vol 2113 (1) ◽  
pp. 012043
Author(s):  
Xinhang Dong ◽  
Boyuan Jing ◽  
Xiang Yang
Keyword(s):  
Integrated Circuits ◽  
Lower Limit ◽  
Critical Path ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Gate Sizing ◽  
Digital Integrated Circuits ◽  
Absolute Value ◽  
Improved Design

Abstract 4-bit absolute-value detector (AVD), as one of the basic implementations of bit arithmetic with logic circuits, can help grab a better understanding about digital integrated circuits. Conventional 4-bit AVDs scheme in a multi-comparator and multiplexers, or need to consider multiple situations of overflow and carry-in, both of which could make the final circuit to be complex, labyrinthine and inefficient in the meantime. In this paper, a new design of 4-bit AVD is proposed, the topology of which includes a 2’s complement calculator and a specially designed logic circuit known as chain carry adder (CCA). The whole circuit is concise and the critical path is rigorously considered to make it as short as possible. The delay is set to 1.5 times its minimum, which is positively corresponding to the length of the critical path, the energy accordingly reaches its lower limit. Gate sizing and Device Voltage (VDD) optimization are proceeded for the exact purpose of proving that the circuit energy is minimized.

scholarly journals Design and Simulation of Linear All-Optical Comparator Based on Square-Lattice Photonic Crystals

2021 ◽  
Author(s):  
Fariborz Parandin ◽  
Reza Kamarian ◽  
Mohamadreza Jomour
Keyword(s):  
Photonic Crystals ◽  
Integrated Circuits ◽  
Photonic Integrated Circuits ◽  
Optical Power ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Square Lattice ◽  
Refractive Indices ◽  
Long Distance ◽  
All Optical

Abstract An optical comparator is an important logic circuit used in digital designs. Photonic crystals are among the platforms for implementing different kinds of gates and logic circuits. Photonic crystals are structures with alternating refractive indices. In digital optics, logical values “0” and “1” are defined based on the level of optical power. In this paper, an optical comparator based on square-lattice photonic crystals is designed and simulated. In the design of this comparator, a small-sized structure is used. The simulation results show that in the proposed comparator, there is a long distance between logical values ​​“0” and “1”. Due to the small size of this comparator and the adequate distance between logical values ​​“0” and “1”, this structure suits photonic integrated circuits with high accuracy.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

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