Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

scholarly journals Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550011
Author(s):  
Neeraja Jagadeesan ◽  
B. Saman ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. Jain
Keyword(s):  
Integrated Circuits ◽  
Quantum Well ◽  
Logic Gates ◽  
Digital Integrated Circuits ◽  
Short Channel ◽  
Flip Flop ◽  
Coupled Channels ◽  
Threshold Voltages ◽  
Sequential Logic ◽  
Quantum Well Devices

The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

scholarly journals Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

2019 ◽  
Vol 8 (3) ◽  
pp. 194
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Energy Efficiency ◽  
Performance Evaluation ◽  
Power Dissipation ◽  
Energy Efficient ◽  
High Speed ◽  
Clock Cycle ◽  
Full Adder ◽  
Majority Gate ◽  
Quantum Dot Cellular Automata ◽  
Gate Count

Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

Energy Efficient Configurable Layout of Logic Block in QCA frame work for an FPGA

2020 ◽  
Vol 12 ◽  
Author(s):  
Arindam Sadhu ◽  
Rimpa Dey Sarkar ◽  
Kunal Das ◽  
Debashis De ◽  
Maitreyi Ray Kanjilal
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Embedded System ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Average Energy ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Logic Block

Aims: Embedded system plays a vital role in today’s life. Hence our motivation is concentrated on area-delay-energy efficient embedded system design in post-CMOS technology i.e. QCA. Objectives: The research is focused on area-delay-energy efficient configurable logic block (CLB) design for field programmable gate array architecture (FPGA) with successful simulation based on a next generation technology, Quantum-dot cellular automata. Methodology: Each proposed circuits are designed in post CMOS 4 dot 2 electron technology i.e. QCA(Quantum Dot Cellular Automata) which has been adopted in circuit implementation due to Low power dissipation, high clock frequency and high package density. Functionality of every circuit is verified by QCADesigner. QCAPro tool is used for power dissipation measurement. Results: In contrast a new approach of using de-multiplexer replacing the decoder has been introduced which results in reduction of the average energy dissipation almost 57%. A NOR based D flip-flop memory architecture and multiplexer is also used in the look up table for the configurable logic block. The proposed architecture thus reduces the overall latency. Proposed CLB is consists of 6356 number of QCA cell with covering 7.44 um2 area. Write and read latency of proposed CLB is 12 and 7.25 QCA clock respectively. Conclusion: The presented paper concludes those read and write latency reduction occurs; average energy dissipation, leakage and switching energy dissipation has been reduced massively and ensues an advantage of overall reduction of the latency for the proposed CLB in the process.

Representative Scan Architecture

2016 ◽  
Vol 25 (05) ◽  
pp. 1650040
Author(s):  
Ling Zhang ◽  
Jishun Kuang
Keyword(s):  
Integrated Circuits ◽  
Test Data ◽  
Switching Activity ◽  
Hardware Cost ◽  
Test Power ◽  
Test Set ◽  
Flip Flop ◽  
Chain Architecture ◽  
Multiple Scan ◽  
Scan Chain

Test power is one of the most challenges faced by Integrated Circuits. The author proposes a general scan chain architecture called Representative Scan (RS). It transforms the scan cells of conventional scan chain or sub-chain into circular shift registers and a representative flip-flop is chosen for each circular shift register, these representative flip-flops are connected serially to setup into the RS architecture. Thus, test data shifting path is shortened, then the switching activity is reduced in the shifting operates. The proposed scan architecture has the similar test power with the multiple scan chain, and only needs same test pins with single scan chain without added test pins. The experimental results show that the proposed scan architecture achieves very low shifting power. For benchmark circuits of ISCAS89, the shifting power of the best architecture of RS is only 0.53%–13.59% of the conventional scan. Especially for S35932, the shifting power on mintest test set is only 0.53% of the corresponding conventional scan. Compared with the conventional scan, the RS only needs to add a multiplexer for each scan cells, and the hardware cost is not high.

A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

2020 ◽  
Vol 15 (1) ◽  
pp. 136-141
Author(s):  
Xianghong Zhao ◽  
Jieyu Zhao ◽  
WeiMing Cai
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
General Structure ◽  
Effective Solution ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Logic Functions ◽  
Structure And Design

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

Material Properties of GaAs-on-Si and Fabrication of Digital Integrated Circuits

1988 ◽  
Vol 116 ◽  
Author(s):  
N. Clhand ◽  
F. Ren ◽  
S. N. G. Chu ◽  
A. M. Sergent ◽  
T. Boone ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Buffer Layer ◽  
Cross Sections ◽  
Power Dissipation ◽  
Propagation Delay ◽  
Si Substrate ◽  
Digital Integrated Circuits ◽  
Lower Growth ◽  
Gaas On Si ◽  
Gaas Buffer Layer

AbstractWe have found that the surface morphology of GaAs grown on Si by MBE is smoother at lower growth temperatures (<500° C), but that the crystalline properties improve at higher growth temperatures (575-600°C). After thermal annealing at 850°C for 15 rai the TEM plan-views indicate that the dislocation density on the surface is reduced by a factor of 4 only. However, the TEM cross-sections indicate a much larger reduction of dislocations in highly dislocated regions near the GaAs/Si interface. Dislocations which are loops or tangles tend to shrink and clean up after annealing leaving a larger volume of GaAs free from, or with fewer, dislocations. The density of electron deep levels reduces with increasing thickness. Electron traps M1, M3 and M4 are not seen when a high purity As is used. For high device performance, the GaAs buffer layer thickness should be at least 2 µm. Although the wafer warpage increases from 7 µm to 52 µm as the GaAs thickness increases from 1.2 µm to 4.2 µm on 7.5 cm wafers, the wafers are as fiat as the original Si wafers under vacuum clamping. Wafer warpage reduced significantly when GaAs was grown selectively through a Si shadow mask. For 1 µm gate MESFET's, σvT was 65 mV on a 3.5 × 3 cm2 wafer area with gmax = 153 mS/ram. A minimum propagation delay of 52 ps/stage at a power dissipation of 1.3 mW/gate was measured for the 19 stage DCFL ring oscillators with 40= yield. Conductivity of the Si substrate and GaAs buffer layer posed no problem in channel isolation. The divide-by-two circuits performed the frequency dividing operation up to 1.8 GHz. The study shows that GaAs-on-Si has a great potential for digital IC's.

scholarly journals Statistical Estimation of the ,Switching Activity in VLSI Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (3) ◽  
pp. 243-254 ◽  
Author(s):  
Farid N. Najm ◽  
Michael G. Xakellis
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Transition Density ◽  
Absolute Error ◽  
Statistical Simulation ◽  
Vlsi Circuits ◽  
Percentage Error ◽  
Circuit Switching ◽  
Low Density ◽  
Switching Activity

Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these problems are directly related to the extent of circuit switching activity. The average number of transitions per second at a circuit node is a measure of switching activity that has been called the transition density. This paper presents a statistical simulation technique to estimate individual node transition densities in combinational logic circuits. The strength of this approach is that the desired accuracy and confidence can be specified up-front by the user. Another key feature is the classification of nodes into two categories: regular- and low-density nodes. Regular-density nodes are certified with user-specified percentage error and confidence levels. Low-density nodes are certified with an absolute error, with the same confidence. This speeds convergence while sacrificing percentage accuracy only on nodes which contribute little to power dissipation and have few reliability problems.

RETIMING SEQUENTIAL CIRCUITS FOR LOW POWER

1996 ◽  
Vol 07 (02) ◽  
pp. 323-340 ◽  
Author(s):  
JOSÉ MONTEIRO ◽  
SRINIVAS DEVADAS ◽  
ABHIJIT GHOSH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Sequential Circuits ◽  
Exact Method ◽  
Switching Activity ◽  
Kolmogorov Equations ◽  
Sequential Circuit ◽  
Clock Period ◽  
Flip Flop ◽  
Combinational And Sequential Circuits

Switching activity is a primary cause of power dissipation in combinational and sequential circuits. In this paper, we present a retiming method that targets the power dissipation of a sequential circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the circuit so as to heuristically minimize weighted switching activities summed over all the gates and flip-flops in the circuit. We extend this method to minimize power dissipation with a specified clock period. For this work we need to obtain efficiently an estimation of the switching activity of every node in the circuit. We give an exact method of estimating power in pipelined sequential circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. This method is significantly more efficient than methods based on solving Chapman–Kolmogorov equations. Experimental results are presented on a variety of circuits.

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